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ICs for Consumer Electronics
TVTEXT 8-Bit Microcontroller, ROMless-Version: SDA 5250 TVTEXT 8-Bit Microcontroller, ROM-Versions: SDA 5251 SDA 5252 SDA 5254 SDA 5255
Preliminary Data Sheet 1998-04-08
SDA 525x Revision History: Previous Version: Page Page (in previous (in current Version) Version)
Current Version: 1998-04-08 User's Manual 06.97 Subjects (major changes since last revision)
The layout of the document has been completely updated.
Edition 1998-04-08 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 525x
Table of Contents 1 2 3 4 4.1 4.2 4.3 4.4 5 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.1.3 6.3.2 6.3.2.1 6.3.2.2 6.3.2.3 6.3.3 6.3.3.1 6.3.4 6.3.4.1
Page
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pin Configuration P-MQFP-80-1 (ROMless-Version) . . . . . . . . . . . . . . . . .8 Pin Configuration P-SDIP-52-1 (ROM-Versions) . . . . . . . . . . . . . . . . . . . . .9 Pin Configuration P-MQFP-64-1 (ROM-Versions) . . . . . . . . . . . . . . . . . . .10 Pin Configuration P-LCC-84-2 (Emulator-Version) . . . . . . . . . . . . . . . . . .11 Pin Functions (ROM- and ROMless-Version) . . . . . . . . . . . . . . . . . . . . .12 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 TTX/VPS Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Acquisition Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Acquisition Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Display Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Display Format and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Display Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Full Screen Background Colour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Clear Page Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Display Page Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 On Screen Display (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Display Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Sandcastle Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 CPU-Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 CPU-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Internal Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
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SDA 525x
Table of Contents 6.3.4.2 6.3.4.3 6.3.4.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.10.1 6.3.10.2 6.3.10.3 6.3.10.4 6.3.10.5 6.3.11 6.3.12 6.3.13 6.3.14 6.3.14.1 6.3.14.2 6.3.14.3 6.3.15 7 7.1 7.2 7.3 8 9 10
Page
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Interrupt Task Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Processor Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Ports and I/O-Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 General Purpose Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Capture Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 More about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 More about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 More about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Pulse Width Modulation Unit (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Analog Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Advanced Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Notes on Data Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Notes on Program Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Instruction Opcodes in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . .122 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 DC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 AC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
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1
General Description
The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acquisition hardware modul, a display generator for "Level 1" TTX data and an 8 bit microcontroller running at 333 ns cycle time. The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX acquisition, transfers data to/from the external memory interface and receives/transmits data via I2C and UART user interfaces. The block diagram shows the internal organization of the SDA 525x. The Slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kbyte. The microcontroller firmware does the total acquisition task (hamming- and parity-checks, page search and evaluation of header control bits) once per field. 2 Features
Acquisition * * * * * * * * Feature selection via special function register Simultaneous reception of TTX, VPS and WSS Fixed framing code for VPS and TTX Acquisition during VBI Direct access to VBI RAM buffer Acquisition of packets X/26, X/27, 8/30 (firmware) Assistance of all relevant checks (firmware) 1-bit framing code error tolerance (switchable)
Display * * * * * * * * * * * * * * * * * Features selectable via special function register 50/60 Hz display Level 1 serial attribute display pages Blanking and contrast reduction output 8 direct addressable display pages for SDA 5250, SDA 5254 and SDA 5255 1 direct addressable display page for SDA 5251 and SDA 5252 12 x 10 character matrix 96 character ROM (standard G0 character set) 143 national option characters for 11 languages 288 characters for X/26 display 64 block mosaic graphic characters 32 characters for OSD in expanded character ROM + 32 characters inside OSD box Conceal/reveal Transparent foreground/background - inside/outside of a box Contrast reduction inside/outside of a box Cursor (colour changes from foreground to background colour) Flash (flash rate 1s)
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* Programmable horizontal and vertical sync delay * Full screen background colour in outer screen * Double size / double width / double height characters Synchronization * Display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with start-stop-oscillator * Independent clock systems for acquisition, display and controller Microcontroller * * * * * * * * * * * * * * * * * * * * * * 8 bit C500-CPU (8051 compatible) 18 MHz internal clock 0.33 s instruction cycle Parallel 8-bit data and 16...19 - bit address bus (ROMless-Version) Eight 16-bit data pointer registers (DPTR) Two 16-bit timers Watchdog timer Capture compare timer for infrared remote control decoding Serial interface (UART) 256 bytes on-chip RAM 8 Kbyte on-chip display-RAM (access via MOVX) for SDA 5250, SDA 5254 and SDA 5255 1 Kbyte on-chip display-RAM (access via MOVX) for SDA 5251 and SDA 5252 1 Kbyte on-chip TVT/VPS-Acquisition-buffer-RAM (access via MOVX) 1 Kbyte on-chip extended-RAM (access via MOVX) for SDA 5250, SDA 5254 and SDA 5255 6 channel 8-bit pulse width modulation unit 2 channel 14-bit pulse width modulation unit 4 multiplexed ADC inputs with 8-bit resolution One 8-bit I/O port with open drain output and optional I2C-Bus emulation (PORT 0) Two 8-bit multifunctional I/O ports (PORT 1, PORT 3) One 4-bit port working as digital or analog inputs (PORT 2) One 2-bit I/O port with optional functions One 3-bit I/O port with optional RAM/ROM address expansion up to 512 Kbyte (ROMless-Version)
- P-SDIP-52-1 Package or P-MQFP-64-1 for ROM-Versions (SDA 5251, SDA 5252, SDA 5254, SDA 5255) - P-MQFP-80-1 Package for ROMless-Version (SDA 5250 M) - P-LCC-84-2 Package for Emulator-Version (SDA 5250) - 5 V Supply Voltage
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3
Block Diagram
CVBS FIL1SLC FIL2SLC FIL3SLC REF
Capture Compare Timer Watchdog Timer VTX, VPS Slicer
TTC Acquisition TTD
Display Timing Character ROM 448 * 12 * 10 Display Generator
VS HS / SC
LCIN LCOUT
R G B BLAN COR
ADC
PWM
C500 CPU
Memory Management Unit (MMU) 2)
Extended Data RAM 1 K Byte 3)
Program Memory ROM 1)
Dual Port Interface
Dual Port Interface Display RAM 4)
VBI Buffer 1 K Byte
P3 P2 P1 P0 XTAL1, XTAL2
RD, WR PSEN, ALE D (7:0) A (16:0) P4.1 (A18), P4.0 (A17)
1) Only ROM Version 2) Only ROMless Version 3) Only SDA 5250, SDA 5254 and SDA 5255 4) 8 KByte for SDA 5250, SDA 5254 and SDA 5255 1 KByte for SDA 5251, SDA 5252
UEB08124
Figure 1 Block Diagram
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4 4.1
Pin Configurations Pin Configuration P-MQFP-80-1 (ROMless-Version)
P0.4 P0.3 P0.2 P0.1 P0.0 VS/P4.7 HS/SC LCOUT LCIN
V DD V SS
50
P0.5 P0.6 P0.7 P2.3 P2.2 P2.1 P2.0
60 61
BLAN B G R D3 D2 D4 D1
41 40 30 21 D5 D0 D6 A0 D7 A1 A2 A10 A3 A4 A11 A5 A9 A6 A8 A7 A13 A12 A14 A15 20
V SSA
FIL3 FIL1 FIL2 70
SDA 5250 M
V DDA
REF
CVBS P3.7 P3.6 P3.5 P3.4 P3.3 P3.2
80 1 10
COR
XTAL2 XTAL1 RST ALE A17 / P4.0 A16 A18 / P4.1
N.C. P3.1 P3.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
V SS V DD
UEP08125
Figure 2 Pin Configuration P-MQFP-80-1 (ROMless-Version) (top view)
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4.2
Pin Configuration P-SDIP-52-1 (ROM-Versions)
P3.1 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41
P3.0 COR BLAN B G R VS / P4.7 HS / SC P3.2 P3.4 P3.5 P3.6 P3.7 LCOUT LCIN
V SS V DD
XTAL1 XTAL2 P4.0 RST P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
SDA 5251 SDA 5252 SDA 5254 SDA 5255
40 39 38 37 36 35 34 33 32 31 30 29 28 27
V DD
P3.3
V SS
P2.0 P2.1 P2.2 P2.3 CVBS
V SSA
FIL3 FIL1
REF
V DDA
FIL2
UEP08126
Figure 3 Pin Configuration P-SDIP-52-1 (ROM-Versions) (top view)
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4.3
Pin Configuration P-MQFP-64-1 (ROM-Versions)
XTAL2
XTAL1 VDD
P1.4
P1.5
P1.6
P1.7
P4.0
P0.0
VDD VSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 N.C. P1.3 P1.2 P1.1 P1.0 VSSA FIL3 FIL1 FIL2 VDDA 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P2.0 2 3 4 5 6 7 LCIN 8 LCOUT 9 10 11 12 13 14 15 16 N.C. N.C. P3.5 P3.2 HS/SC P3.7 P3.6 P3.4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 N.C. P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P3.1 P3.0 COR BLAN B G R VS/P4.7 N.C.
SDA 5251M SDA 5252M SDA 5254M SDA 5255M
I REF
CVBS P2.3 P2.2 P2.1 N.C.
P3.3 VDD
VSS VSS
VDD
VSS
P0.1
RST
N.C.
N.C.
UEP09858
Figure 4 Pin Configuration P-MQFP-64-1 (ROM-Versions) (top view)
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4.4
Pin Configuration P-LCC-84-2 (Emulator-Version)
53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P0.6 P0.7 STOP_OCF ENE P2.3/ANA3 P2.2/ANA2 P2.1/ANA1 P2.0/ANA0 VSSA FIL3 FIL1 FIL2 VDDA REF CVBS P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 D5 D0 D6 A0 D7 A1 A2 A10 A3 PSEN A4 A11 A5 A9 A6 A8 A7 A13 A12 A14 A15
75 76 77 78 79 80 81 82 83 84
P3.1 P3.0/ODD-EVEN P1.7 P1.6 P1.5 P1.4 P1.3
P1.2
P1.1 P1.0 VSS VDD XTAL2 XTAL1 RST WR RD ALE A17/P4.0 A16 A18/P4.1
P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 VS /P4.7/ODD-EVEN HS/SC LCOUT LCIN VDD VSS COR BLAN B G R D3 D2 D4 D1
SDA 5250
1 3 4 5 6 7 8 9 10 11
UEP10154_B
Figure 5 Pin Configuration P-LCC-84-2 (Emulator-Version) (top view)
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5
Pin Functions (ROM- and ROMless-Version)
Table 1 Pin Functions (ROM- and ROMless-Version)
Symbol Pin No. P-SDIP52-1 Pin No. P-MQFP64-1 Pin No. P-MQFP80-1 Pin No. Input (I) Function P-LCC-84- Output (O) 2 Supply (S)
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
9 8 7 6 5 4 3 2 23 22 21 20 19 18 17 16
34 33 31 30 29 28 27 26 53 52 51 50 48 47 46 44
56 57 58 59 60 61 62 63 11 10 9 8 7 6 5 4
48 49 50 51 52 53 54 55 84 83 82 81 80 79 78 77
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Port 0 is an 8-bit open drain bidirectional I/O port. Port 0 pins that have 1s written to them float; in this state they can be used as highimpedance inputs (e.g. for software driven I2C Bus).
Port 1 is an 8-bit bidirectional multifunctional I/O port with internal pullup resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs. The secondary functions of port 1 pins are: Port bits P1.0 - P1.5 contain the 6 output channels of the 8-bit pulse width modulation unit. Port bits P1.6 - P1.7 contain the two output channels of the 14-bit pulse width modulation unit. P2.0 - P2.3 are working as digital or analog inputs.
P2.0 P2.1 P2.2 P2.3
34 33 32 31
1 63 62 61 40
67 66 65 64 14
61 60 59 58 3
I I I I O
XTAL2 13
Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left open. Input to the inverting oscillator amplifier A low level on this pin resets the processor
XTAL1 12 RST 15
39 42
15 16
4 5
I I
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Table 1 Pin Functions (ROM- and ROMless-Version) (cont'd)
Symbol Pin No. P-SDIP52-1 Pin No. P-MQFP64-1 Pin No. P-MQFP80-1 Pin No. Input (I) Function P-LCC-84- Output (O) 2 Supply (S)
VDD VSS
R G B BLAN COR P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
11, 37 10, 35 47 48 49 50 51 52 1 44 36 43 42 41 40
5, 6, 37, 38 2, 3, 35, 36 19 20 21 22 23 24 25 15 4 14 13 10 9
13, 51 12, 50 45 46 47 48 49 3 2 80 79 78 77 76 75
2, 43 1, 42 37 38 39 40 41 76 75 74 73 72 71 70 69
S S O O O O O I/O I/O I/O I/O I/O I/O I/O I/O
Power supply voltage Ground (0 V) Red colour signal output Green colour signal output Blue colour signal output Blanking output Contrast Reduction output Port 3 is an 8-bit bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs. It also contains the interrupt, timer and serial port input pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3 as follows: - INT0 (P3.2): interrupt 0 input/timer 0 gate control input - INT1 (P3.3): interrupt 1 input/timer 1 gate control input - T0 (P3.4): counter 0 input - T1 (P3.5): counter 1 input - RXD(P3.6): serial port receive line - TXT(P3.7): serial port transmit line Attention: P3.6 must not be kept to `0' during reset, otherwise a special test mode will be activated.
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Table 1 Pin Functions (ROM- and ROMless-Version) (cont'd)
Symbol Pin No. P-SDIP52-1 Pin No. P-MQFP64-1 Pin No. P-MQFP80-1 Pin No. Input (I) Function P-LCC-84- Output (O) 2 Supply (S)
HS/SC 45 VS/P4.7 46 CVBS P4.0 P4.1 30 14 -
16 18 60 41 -
54 55 74 18 20
46 47 68 9 11
I I/O I I/O I/O
Horizontal sync input (alternative sandcastle sync input) for display Vertical sync input for display (alternative Port 4.7) CVBS (video signal) input Port 4.0 is a bidirectional I/O port with internal pullup resistors. Port 4 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs. Attention: P4.0 must not be kept to `0' during reset, otherwise a special test mode will be activated. Reference current input for slicer PLLS Analog Supply Voltage for Slicer and ADC Analog Ground for Slicer and ADC PLL loop filter I/O for TTX slicing PLL loop filter I/O for VPS/WSS slicing PLL loop filter I/O for TTX/VPS/WSS data slicing LCIN and LCOUT are used to connect the external display dot clock frequency reference.
IREF VDDA VSSA
FIL1 FIL2 FIL3
29 28 24 26 27 25
59 58 54 56 57 55 7 8
73 72 68 70 71 69 52 53
67 66 62 64 65 63 44 45
I S S I/O I/O I/O I O
LCIN 38 LC-OUT 39
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Table 2 Additional PINS for ROMless-Version
Symbol Pin Nr. P-MQFP-80-1 37 35 34 32 31 29 27 25 26 28 33 30 23 24 22 21 19 39 41 43 44 42 40 38 36 - - - - 17 - Pin Nr. P-LCC-84-2 29 27 26 24 22 20 18 16 17 19 25 21 14 15 13 12 10 31 33 35 36 34 32 30 28 56 57 7 6 8 23 Input (I) Output (O) Supply (S) O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O O O Function
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 STOP_OCF ENE RD WR ALE PSEN
Address bus for external memory
Data bus for external memory
Control Signals for data memory extension and emulation.
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6 6.1 6.1.1
Functional Description Acquisition TTX/VPS Slicer
The slicer extracts horizontal and vertical sync information and TTX data from the CVBS signal. The slicer includes an analog circuit for sync filtering and data slicing. Further there are two analog PLLs for system clock generation for both TTX and VPS. Therefore the slicer is able to receive both TTX and VPS in succeeding lines of a vertical blanking interval. A third data-PLL shifts the phase of the system clock for data sampling. The internal slicer timing signals are generated from the VPS-PLL. 6.1.2 Acquisition Hardware
The acquisition hardware transforms the sliced bit stream into a byte stream. A framing code check follows to identify a TTX or VPS line. If the framing code error tolerance is enabled then one-bit errors will be allowed. For each line in the VBI in which a framingcode is detected, a maximum of 42 bytes (VPS: 26 bytes) plus a status word are stored in the VBI-buffer. After framing code detection a status word is generated which informs about the type of data received (TTX or VPS) and the signal quality of the TV channel. Chapter "Acquisition Status Word" on page 17 shows the format of this status word. The horizontal and vertical windows in which TTX or VPS data are accepted and checked for framing code errors are generated automatically. The VBI buffer data will be analyzed (Hamming, parity and acquisition) by the microcontroller and stored in the dual port display RAM or the external RAM, if selected. This analysis is repeated for every field.
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Acquisition Status Word TTX/VPS FCER FCOK LIN.4 LIN.3 LIN.2 LIN.1 LIN.0
LIN.(4...0)
number of TV line in which data was received. This information can be used to realize a "software data entry window". 6 LIN. (4...0) 22 1 = Framing code OK (VPS or TTX). This bit is set always by hardware, because lines with valid framing codes are stored only. This bit is reset by software in VBI-buffer. If reset, it indicates that this line was already processed. 1 = The framing code for TTX lines was accepted with 1-biterror. For VPS lines this bit has no meaning. 0 = For TTX lines the framing code E4H was detected. 1 = A valid TTX framing code was detected and the data-PLL is locked to the TTX frequency. 0 = A valid VPS framing code was detected and the data-PLL is locked to the VPS frequency. Memory Interface
FCOK
FCER
TTX/VPS
6.1.3
The acquisition dual port interface manages the VBI memory write access request from the acquisition hardware and an asynchronous memory access request from the microcontroller. The acquisition hardware delivers the address and data and then a request to the interface. The access of acquisition hardware and controller is under a special arbiter control. The end of data is indicated by the bit LIN24ST in SFR ACQSIR.
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6.1.4
Acquisition Control Registers
The following sections gives an overview about special function registers ACQMS_1, ACQMS_2 and ACQSIR, with which slicer and acquisition can be controlled: Acquisition Mode and Status Register ACQMS_1 Acquisition Mode and Status Register Default after reset: 00H (MSB) 0 0 VPSE 0 CRIC.1 CRIC.0 ENERT (LSB) TTXE ACQMS_1 SFR-Address C1H
TTXE ENERT CRIC.1 ... CRIC.0
1: 1: 00: 01: 10: 11: 1:
enable TTX in lines 6 - 22 allow 1 bit error for TTX The CRI is not included in FRC last 2 bits of CRI are included in the FRC last 4 bits of CRI are included in the FRC last 8 bits of CRI are included in the FRC enable VPS in line 16. Text-reception in this line is automatically disabled
VPSE Comments
Bits 4, 6 and 7 are not defined, must be set to 0
Acquisition Mode and Status Register ACQMS_2 Acquisition Mode and Status Register Default after reset: 00H (MSB) TEST.7 TEST.6 TEST.5 TEST.4 TEST.3 TEST.2 TEST.1 (LSB) TEST.0 ACQMS_2 SFR-Address C2H
Comments
all bits have to be set to 0. Setting any of these bits will switch on special slicer test modes for production test
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Acquisition-Sync-Interrupt-Register ACQSIR Acquisition-Sync-InterruptRegister Default after reset: 00H (MSB) EVENEN EVENST LIN24EN LIN24ST AVIREN AVIRST AHIREN (LSB) AHIRST ACQSIR SFR-Address C0H
AHIRST AHIREN AVIRST AVIREN LIN24ST
1 = acquisition horizontal sync interrupt request. This bit is set by the positive edge of HS. It must be reset by software. 1 = enable acquisition horizontal sync interrupt request. 1 = acquisition vertical sync interrupt request. This bit is set by the positive edge of VS. It must be reset by software. 1 = enable acquisition vertical sync interrupt request. 1 = acquisition line 24 interrupt request. Acquisition hardware processing in VBI interval is finished. This bit assists the synchronization of acquisition software to the ACQTiming. It is set by hardware at the beginning of line 24 and the corresponding line of 2nd field. It is reset by software. 1 = enable acquisition line 24 interrupt request. 1 = even field interrupt. Must be reset by software. 1 = enable even field interrupt requests. None
LIN24EN EVENST EVENEN Comments
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6.2
Display Generator
The display features of SDA525x are similar to the Siemens SDA5248 TTX controller. The display generator reads character addresses and control characters from the display memory, selects the pixel information from the character ROM and translates it into RGB values corresponding to the World Standard Teletext Norm. The national option character bits for 11 languages inclusive X/26 characters are also supported. 6.2.1 Display Format and Timing
A page consists of 25 rows of 40 characters each. One character covers a matrix of 12 horizontal and 10 vertical pixels. The pixel frequency should be 12 MHz corresponding to 1 s for one character and 40 s for one row. A total of 250 TV lines are used for TTX display. The display can be shifted horizontally from 0 s to 21.33 s with respect to HS and vertically from line 1 (314) to line 64 (377) with respect to VS. The display position is determined by the registers DHD and DVD.
Note: To avoid interferences between the subharmonics of the 18 MHz controller clock and the 12 MHz pixel clock, a pixel clock of about 11,5 MHz is recommended.
6.2.2 Display Cursor
A cursor is available which changes foreground to background colour for one character. Cursor flash can be realized via software enabling/disabling the cursor. The cursor position is defined by cursor position registers DCRP and DCCP. 6.2.3 Flash
A character background flash (character is changed to background colour) is realized by hardware. The flash frequency is 1 Hz with a duty cycle of 32:18. 6.2.4 Full Screen Background Colour
The SDA 525x delivers the new full screen background colour feature. Special function register SFR DTIM(7-5) includes three bits which define the default background colour for the inner and outer screen area. 6.2.5 Clear Page Logic
The clear page logic generates a signal which is interpreted by the character generator to identify non displayable rows. In row 25 specific information is stored by the microcontroller indicating which of the rows 0 - 24 should be interpreted as erased during character generation. At the beginning of each row the special control characters are read from the display memory (see Table 3).
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Table 3 Clear Page Bits row 25 /column: 0 1 2 3 ER24...ER0 = 1: ER24...ER0 = 0: 6.2.6 D7 ER7 ER15 ER23 0 D6 ER6 ER14 ER22 0 D5 ER5 ER13 ER21 0 D4 ER4 ER12 ER20 0 D3 ER3 ER11 ER19 0 D2 ER2 ER10 ER18 0 D1 ER1 ER9 ER17 0 D0 ER0 ER8 ER16 ER24
row is interpreted as a blanked row row is received and displayed
Display Page Addressing
The display generator hardware generates a row/column address for the display memory. Because there is a binary to row/column address translation between display generator and memory, the OSD programmer has to take care of this. The relationship between row/column and binary address in memory is shown in Table 4. Table 4 Row/Column to Binary Translation Table C0 Row0 Row1 . . . Row23 Row24 Row25 00H 20H . . . 2E0H 300H 320H ... ... ... . . . ... ... ... C31 1FH 3FH . . . 2FFH 31FH 337H C32 3F8H 3F0H . . . 340H 338H ... ... ... . . . ... ... C39 3FFH 3F7H . . . 347H 33FH
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6.2.7
Character Generator
The character generator includes the character and control code decoder, the RAM interface and the RGB-, BLAN- and COR-signal generator. The display generator reads data from the display RAM and calculates appropriate data which drives the RGB output pins. The pixel clock is generated by a start-stop-oscillator. The synchronization of display and pixel clock is done via external sandcastle or HS and VS signals. For 60 Hz display the number of lines per character can be reduced to 9 or 8. In this case pixel information of line 10 or 9 plus 10 are rejected. With this mode combined with the variable vertical offset it is possible to generate NTSC displays with 25 rows. Characters with a binary value < 32 are interpreted as control characters. For binary values 32 a ROM character is selected through the addition of the character address, the language setting in SFR, the europe designation and the graphics control bits delivered from the control bit decoder. A total of 64 OSD characters and 64 mosaic graphics characters are available. OSD characters with addresses 80...SFH can be displayed together with 60 lower case characters because there is no memory overlapping with any other characters. OSD characters with addresses 60...7FH can only be displayed if bit OSD in SFR LANGC is set (see diagrams: Physical Address Space and Vertical Address Space). Figures 6 - 13 shows the character ROM contents. The control byte decoder analyses the serial attributes from the display memory and generates control clocks for the RGB logic and the character address decoder. The interpretation of control characters is corresponding to World Standard Teletext norm. Table 5 shows the characters and the appearance on the screen. The RGB logic combines data from the character address decoder, control byte decoder and settings from the SFR registers and generates signal R, G, B, BLAN and COR. 6.2.8 On Screen Display (OSD)
A display page in the display memory can also be used for on screen displays. It should be recognized that all serial attributes of a normal text page are also valid for an OSD display. Therefore if double height is selected anywhere in a normal text page, row n and row n-1 (upper row) should be saved and overwritten by OSD data in order to generate a correct display. Switching back to text display is accomplished by rewriting the text data to the page. The same procedure is needed for the "erase row bits" in row 25. By means of enable box bits, transparent control bits and the serial attribute "OSD", the OSD screen can be controlled fully independent of the normal text page. The serial OSD-bit toggles the screen between normal display and OSD.
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Table 5 Serial Control Bytes B7, B6, B5, B4 B3, B2, B1, B0 0 1 2 3 4 5 6 7 8 9 A B C D E F
(1) (2) (3)
0 Alpha Black Alpha Red Alpha Green Alpha Yellow Alpha Blue Alpha Magenta Alpha Cyan Alpha White Flash Steady(1,2) End Box (1,3) Start Box (3) Normal Height(1,2) Double Height Double Width(4) Double Size(4)
(1)
1 Mosaic Black Mosaic Red Mosaic Green Mosaic Yellow Mosaic Blue Mosaic Magenta Mosaic Cyan Mosaic White Conceal(2) Contiguous Mosaic(1,2) Separated Mosaic(2) OSD(5) Black Background(2) New Background (2) Hold Mosaic(2) Release Mosaic(1)
(4) (5)
Reset state at begin of each row. Takes effect with control character. Other control characters takes effect in the next character field. Two identical control characters are transmitted in sequence. The effect begins between the control characters. Can only be activated if SFR DMOD.0 is set to `1', otherwise no influence. Toggle; takes effect with next character (on), takes effect with control character (off).
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6.2.9
Display Special Function Registers
The display generator includes 9 registers to select the different formats and functions. Display Horizontal Delay Register DHD Display Horizontal Delay Register Default after reset: 00H (MSB) HD.7 HD.6 HD.5 HD.4 HD.3 HD.2 HD.1 (LSB) HD.0 DHD SFR-Address C3H
HD.7 ... HD.0 Comments
variable negative horizontal display offset relative to positive edge of HS in pixel units. None
Display Vertical Delay Register DVD Display Vertical Delay Register Default after reset: 00H (MSB) - - VD.5 VD.4 VD.3 VD.2 VD.1 (LSB) VD.0 DVD SFR-Address C4H
VD.5 ... VD.0 Comments
variable negative vertical display offset relative to positive edge of VS in HS units. None
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Display Transparent Control Register DTCR Display Transparent Control Register Default after reset: 00H (MSB) CORI CORO ICRP IBP TRFI TRFO TRBI (LSB) TRBO DTCR SFR-Address C5H
TRBO TRBI TRFO TRFI IBP ICRP CORO CORI
1 = Transparent Background Colors outside Box and OSD. 1 = Transparent Background Colors inside Box or OSD. 1 = Transparent Foreground Colors outside Box and OSD. 1 = Transparent Foreground Colors inside Box or OSD. 1 = Invert Blanking Polarity. Blanking is active high. 0 = Blanking is active low. 1 = Invert Contrast Reduction Polarity. COR is active high. 0 = COR is active low. 1 = Contrast Reduction for Background Color outside Box and outside OSD. 1 = Contrast Reduction for Background Color inside Box or inside OSD.
Note: Outside of a box means outside of a box opened by control code sequence `0B,0B' and outside of an OSD-Box opened by control code `1B'. Inside a box means inside of a box opened by control code sequence `0B,0B' or inside an OSD-Box opened by control code `1B'.
Comments For further Transparent Modes see SFR DCRP.
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Display Mode Register DMOD Display Mode Register Default after reset: XXXX0000B (MSB) - - - - 0 0 0 (LSB) DSDW DMOD SFR-Address D6H
DSDW
if set, displaying Double Size and Double Width characters is enabled if cleared, control codes 0EH and 0FH have no effect have always to be written with `0' not implemented, to be written with `0'
Bit 1 to 3 Bit 4 to 7
Note: This register is not readable. Thus, do not use read-modify-write operations like ANL, ORL to modify this register.
Display Feature Double Size and Double Width Double Size and Double Width are selectable via serial attributes. The control codes are `0E' for Double Width and `0F' for Double Size. Now, there are 4 control codes available, to modify the character size: Control Name Code 0C 0D 0E 0F Normal Size Double Height Double Width Double Size Effect No stretching Vertical character stretching Horizontal character stretching Horizontal and vertical stretching Side Effects any activated stretching off horizontal stretching off vertical stretching off None
Since Double Width and Double Size control codes should not be interpreted by a pure level 1 text-decoder, this size attributes have to be enabled by setting SFR-bit DSDW. Double Width and Double Size characters are accomplished by skipping every second character code after setting any of this following attributes where the remaining displayable characters are stretched horizontally and thus conceating the character. Although every second character is hidden, these codes will take effect if they are control characters.
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Display Mode Register 1 DMODE1 Display Mode Register 1 Default after reset: 00H (MSB) ST_TOP ST_DIS CON DH.1 DH.0 BD_24 BD_1_23 (LSB) BD_0 DMODE1 SFR-Address C6H
BD_0 BD_1_23 BD_24 DH.1 ... DH.0
1 = Box characters in row 0 are ignored. 0 = Box characters in row 0 are displayed. 1 = Box characters in row 1 - 23 are ignored. 0 = Box characters in row 1 - 23 are displayed. 1 = Box characters in status row are ignored. 0 = Box characters in status row are allowed. 00 = Normal row display. 01 = Rows 0 - 11 are displayed in double height. Status row is displayed in normal height. 10 = Rows 12 - 23 are displayed in double height. Status row is displayed in normal height. 11 = Not defined. 1 = Concealed characters are visible. 0 = Concealed characters are not visible. 1 = Status row is handled as blanked row. 0 = Status row is displayed. 1 = Status row is displayed in row 0 of display. 0 = Status row is displayed in row 24 of display. Only boxes opened by the control code sequence 0BH, 0BH will be influenced, an OSD-Box (opened by control code 1BH) will not be affected.
CON ST_DIS ST_TOP Comments
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Display Mode Register 2 DMODE2 Display Mode Register 2 Default after reset: 00H (MSB)
DTEST.2 DTEST.1 DTEST.0 DCHAP.2 DCHAP.1 DCHAP.0 C10
DMODE2
SFR-Address C7H (LSB)
C7
C7 C10 DCHAP.2..0 DTEST.0 DTEST.1 DTEST.2 Comments
1 = Header is handled as erased row (Suppress Header). 1 = Rows 1 - 23 are handled as erased rows (Inhibit Display). selects one of eight display chapters. Not defined, must be set to 0. Not defined, must be set to 0. Not defined, must be set to 0. For 1-page-versions (SDA 5251, SDA 5252) the bits DCHAP.2..0 have to be set to `0'.
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Language Control Register LANGC Language Control Register Default after reset: 00H (MSB)
OSD_64 LANGC.6 LANGC.5 LANGC.4 LANGC.3 LANGC.2 LANGC.1
LANGC
SFR-Address C9H (LSB)
LANGC.0
LANGC.4... LANGC.0
Language selection for text outside of an OSD window. 00000 : German 01010 : English 01011 : Scandinavian 01100 : Italian 01101 : French 01110 : Spanish 11001 : Turkish 11010 : Rumanian 11011 : Hungarian 11100 : Czechish 11101 : Polish 11110 : Serbian others : Not defined 00: West european special characters are addressable. 01: West european special characters are addressable (Turkish). 10: East european special characters are addressable. 11: Not defined. 1: 64 OSD character mode on. If the serial attribute OSD is set a total of 64 OSD characters is available. The lower case G0 characters can not be used. 32 OSD character mode on. Only OSD characters in ROM column 8 and 9 are available if serial attribute OSD is set. Outside an OSD box all 64 OSD characters are available (see Figure 12).
LANGC.6... LANGC.5
OSD_64
0:
Comments
see Diagrams `x' and `y' Physical and Vertical address spaces
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Display Cursor Column Position Register DCCP Display Cursor Column Position Register Default after reset: 00H (MSB) - DC_EN DCCP.5...DCCP.0 Bit 7 Comments DC_EN DCCP.5 DCCP.4 DCCP.3 DCCP.2 DCCP.1 (LSB) DCCP.0 DCCP SFR-Address CAH
1 = Display Cursor Enable. 0 = Display Cursor Disable. Active cursor column position. DCCP.5...0 = 0D: column 1 on screen. reserved, should be set to `0'. None
Display Cursor Row Position Register DCRP Display Cursor Row Position Register Default after reset: 00H (MSB) TRBOS COROS - DCRP.4 DCRP.3 DCRP.2 DCRP.1 (LSB) DCRP.0 DCRP SFR-Address CBH
DCRP.4...DCRP.0 TRBOS
defines row of active cursor position. 1 = The outer screen display area appears transparent 0 = The outer screen display area gets the background colour defined in register DTIM 1 = Contrast reduction outer screen reserved, should be set to `0'. bits TRBOS and COROS thematically belong to the SFR DTCR
COROS Bit 5 Comments
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Display Timing Control Register DTIM Display Timing Control Register Default after reset: 00H (MSB) BG_R BG_G BG_B EO_P30 EO_VS SANDC LIN9 (LSB) LIN8 DTIM SFR-Address CCH
LIN8 LIN9 SANDC
EO_VS
EO_P30 BG_R BG_G BG_B
1 = 8 line character mode (higher priority than LIN9). 1 = 9 line character mode. 1 = horizontal and vertical synchronization accepts sandcastle pulse from pad HS/SC. 0 = horizontal and vertical synchronization accepts HS and VS pulses from pads HS/SC and VS respectively. 1 = The ODD/EVEN-signal evaluated from CVBS is enabled on Pin VS. 0 = ODD/EVEN function is disabled. 1 = The ODD/EVEN-signal evaluated from CVBS is enabled on Pin P3.0. 0 = ODD/EVEN function is disabled. BG_R BG_G BG_B black red green blue 0 1 0 0 0 0 1 0 0 0 0 1 BG_R BG_G BG_B yellow 1 violet cyan white 1 0 1 1 0 1 1 0 1 1 1
outer screen background colour
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Teletext-Sync-Interrupt-Register TTXSIR Teletext-Sync-InterruptRegister Default after reset: 00H (MSB) - VSY HSY PCLK DVIREN DVIRST DHIREN (LSB) DHIRST TTXSIR SFR-Address C8H
DHIRST DHIREN DVIRST DVIREN PCLK HSY VSY
1 = display horizontal sync interrupt request (set by positive edge of HS, reset by software). 1 = enable display horizontal sync interrupt requests. 1 = display vertical sync interrupt request (set by positive edge of VS, reset by software). 1 = enable display vertical sync interrupt requests. Reflects state of internal pixel clock. Reflects state of HS-signal decoded by SC-decoder Reflects state of VS-signal decoded by SC-decoder (SANDC=1). Reflects state of VS-pin (SANDC=0). reserved, should be set to `0'
Bit 7
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6.2.10
Sandcastle Decoder
To fit the requirements of various applications the input circuit of the sandcastle decoder is programmable. Both slicing levels (VSCH, VSCL2) which are important for proper SCdecoder function can be varied in a range of about 0.9 V and in addition there is the possibility to increase the implemented hysteresis by 0.3 V typically. Further noise reduction and spike rejection on pin SC is accomplished by using a digital filter following the input circuitry. See Figure 41 on page 133 for further information on VSCH and VSCL2. Sandcastle Control Register SCCON Sandcastle Control Register Default after reset: 00H (MSB) 0 SCCH.2 SCCH.1 SCCH.0 0 SCCL.2 SCCL.1 (LSB) SCCL.0 SCCON SFR-Address CEH
SCCL1...0
00 = set VSCL2 to lowest level (1.0 V typ.) 01 = increase VSCL2 by 0.3 V (typ.) 10 = increase VSCL2 by 0.6 V (typ.) 11 = increase VSCL2 by 0.9 V (typ.) 0 = hysteresis VSCL2 set to 0.3 V (typ.) 1 = increase hysteresis VSCL2 by 0.6 V (typ.) 00 = set VSCH to lowest level 3.0 V (typ.) 01 = increase VSCH by 0.3 V (typ.) 10 = increase VSCH by 0.6 V (typ.) 11 = increase VSCH by 0.9 V (typ.) 0 = hysteresis VSCH set to 0.3 V (typ.) 1 = increase hysteresis VSCH by 0.6 V Bits 3 and 7 have to be set to `0'.
SCL.2 SCCH1...0
SCCH.2 Attention
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2/0 2/1 2/2 2/3 NO 2/4 NO 2/5 2/6 2/7 2/8
3/0 3/1 3/2 3/3 3/4 3/5 3/6 3/7 3/8
4/0 NO 4/1 4/2 4/3 4/4 4/5 4/6 4/7 4/8
5/0 5/1 5/2 5/3 5/4 5/5 5/6 5/7 5/8
6/0 NO 6/1 6/2 6/3 6/4 6/5 6/6 6/7 6/8
7/0 7/1 7/2 7/3 7/4 7/5 7/6 7/7 7/8
2/9 2/A 2/B 2/C
3/9 3/F 3/B 3/C 3/D 3/E 3/F
4/9 4/A 4/B 4/C 4/D 4/E 4/F
5/9 5/A 5/B NO 5/C NO 5/D NO 5/E NO 5/F NO
6/9 6/A 6/B 6/C 6/D 6/E 6/F
7/9 7/A 7/B NO 7/C NO 7/D NO 7/E NO 7/F
UED08127
2/D
2/E 2/F
Figure 6 G0 Character Set
Note: NO = hardware mapped national option character
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A/0 A/1 A/2 A/3 A/4 A/5 A/6 A/7 A/8
B/0 B/1 B/2 B/3 B/4 B/5 B/6 B/7 B/8
C/0 C/1 C/2 C/3 C/4 C/5 C/6 C/7 C/8
D/0 D/1 D/2 D/3 D/4 D/5 D/6 D/7 D/8
E/0 E/1 E/2 E/3 E/4 E/5 E/6 E/7 E/8
F/0 F/1 F/2 F/3 F/4 F/5 F/6 F/7 F/8
A/9 A/A A/B A/C A/D A/E A/F
B/9 B/A B/B B/C B/D B/E B/F
C/9 C/A C/B C/C C/D C/E C/F
D/9 D/A D/B D/C D/D D/E D/F
E/9 E/A E/B E/C E/D E/E E/F
F/9 F/A F/B F/C F/D F/E F/F
UED08128
Figure 7 Character Set West Europe
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A/0 A/1 A/2 A/3 A/4 A/5 A/6 A/7 A/8
B/0 B/1 B/2 B/3 B/4 B/5 B/6 B/7 B/8
C/0 C/1 C/2 C/3 C/4 C/5 C/6 C/7 C/8
D/0 D/1 D/2 D/3 D/4 D/5 D/6 D/7 D/8
E/0 E/1 E/2 E/3 E/4 E/5 E/6 E/7 E/8
F/0 F/1 F/2 F/3 F/4 F/5 F/6 F/7 F/8
A/9 A/A A/B A/C A/D A/E A/F
B/9 B/A B/B B/C B/D B/E B/F
C/9
D/9 D/A D/B D/C D/D D/E D/F
E/9 E/A E/B E/C E/D E/E E/F
F/9 F/A F/B F/C F/D F/E F/F
UED08129
C/A C/B C/C C/D C/E C/F
Figure 8 Character Set West Europe (Turkish)
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A/0 A/1 A/2 A/3 A/4 A/5 A/6 A/7 A/8
B/0 B/1 B/2 B/3 B/4 B/5 B/6 B/7 B/8
C/0 C/1 C/2 C/3 C/4 C/5 C/6 C/7 C/8
D/0 D/1 D/2 D/3 D/4 D/5 D/6 D/7 D/8
E/0 E/1 E/2 E/3 E/4 E/5 E/6 E/7 E/8
F/0 F/1 F/2 F/3 F/4 F/5 F/6 F/7 F/8
A/9 A/A A/B A/C A/D A/E A/F
B/9 B/A B/B B/C B/D B/E B/F
C/9
D/9 D/A D/B D/C D/D D/E D/F
E/9 E/A E/B E/C E/D E/E E/F
F/9 F/A F/B F/C F/D F/E F/F
UED08130
C/A C/B C/C C/D C/E C/F
Figure 9 Character Set East Europe
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German 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
English
Scandinavian 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
Italian 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
French
Spanish 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
UED08131
Figure 10 National Option Characters I
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Turkish 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
Polish
Czechian 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
Romanian 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
Serbian 2/3 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
7/B 7/C 7/D 7/E
UED08132
Figure 11 National Option Characters II
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6/0 6/1 6/2 6/3 6/4 6/5 6/6 6/7 6/8
7/0 7/1 7/2 7/3 7/4 7/5 7/6 7/7 7/8
8/0 8/1 8/2 8/3 8/4 8/5 8/6 8/7 8/8
9/0 9/1 9/2 9/3 9/4 9/5 9/6 9/7 9/8
6/9 6/A 6/B 6/C 6/D 6/E 6/F
7/9 7/A 7/B 7/C 7/D 7/E 7/F
8/9 8/A 8/B 8/C 8/D 8/E 8/F
9/9 9/A 9/B 9/C 9/D 9/E 9/F
UED08133
Figure 12 OSD Characters Set (these characters are customized and thus left blank on this page)
Note: Characters ... to ... can only be used inside an OSD box.
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2/0 2/1 2/2 2/3 2/4 2/5 2/6 2/7 2/8
3/0 3/1 3/2 3/3 3/4 3/5 3/6 3/7 3/8
6/0 6/1 6/2 6/3 6/4 6/5 6/6 6/7 6/8
7/0 7/1 7/2 7/3 7/4 7/5 7/6 7/7 7/8
2/9 2/A 2/B 2/C
3/9 3/F 3/B 3/C 3/D 3/E 3/F
6/9 6/A 6/B 6/C 6/D 6/E 6/F
7/9 7/A 7/B 7/C 7/D 7/E 7/F
UED08134
2/D
2/E 2/F
Figure 13 Graphics Character Set
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6.3 6.3.1
Microcontroller Architecture
The CPU manipulates operands in two memory spaces: the program memory space, and the data memory space. The program memory address space is provided to accommodate relocatable code. The data memory address space is divided into the 256-byte internal data RAM, XRAM (extended data memory, accessible with MOVX-instructions) and the 128-byte Special Function Register (SFR) address spaces. Four register banks (each bank has eight registers), 128 addressable bits, and the stack reside in the internal data RAM. The stack depth is limited only by the available internal data RAM. It's location is determined by the 8-bit stack pointer. All registers except the program counter and the four 8-register banks reside in the special function register address space. These memory mapped registers include arithmetic registers, pointers, I/O-ports, registers for the interrupt system, timers, pulse width modulator and serial channel. Many locations in the SFR-address space are addressable as bits. Note that reading from unused locations within data memory will yield undefined data. Conditional branches are performed relative to the 16 bit program counter. The registerindirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location in the memory address space. The processor as five methods for addressing source operands: register, direct, registerindirect, immediate, and base-register plus index-register indirect addressing. The first three methods can be used for addressing destination operands. Most instructions have a "destination, source" field that specifies the data type, addressing methods and operands involved. For operations other than moves, the destination operand is also a source operand. Registers in the four 8-register banks can be accessed through register, direct, or register-indirect addressing; the lower 128 bytes of internal data RAM through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through registerindirect addressing; and the special function registers through direct addressing. Lookup tables resident in program memory can be accessed through base-register plus index-register indirect addressing.
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6.3.1.1
CPU-Hardware
Instruction Decoder Each program instruction is decoded by the instruction decoder. This unit generates the internal signals that control the functions of each unit within the CPU-section. These signals control the sources and destination of data, as well as the function of the Arithmetic/Logic Unit (ALU). Program Control Section The program control section controls the sequence in which the instructions stored in program memory are executed. The conditional branch logic enables conditions internal and external to the processor to cause a change in the sequence of program execution. The 16-bit program counter holds the address of the instruction to be executed. It is manipulated with the control transfer instructions listed in Chapter "Instruction Set" on page 116. Internal Data RAM The internal data RAM provides a 256-byte scratch pad memory, which includes four register banks and 128 direct addressable software flags. Each register bank contains registers R0 - R7. The addressable flags are located in the 16-byte locations starting at byte address 32 and ending with byte location 47 of the RAM-address space. In addition to this standard internal data RAM the processor contains an extended internal RAM. It can be considered as a part of an external data memory. It is referenced by MOVX-instructions (MOVX A, @DPTR), the memory map is shown in Figure 21. Arithmetic/Logic Unit (ALU) The arithmetic section of the processor performs many data manipulation functions and includes the Arithmetic/Logic Unit (ALU) and the A, B and PSW-registers. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations of add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust and compare, and the logic operations of and, or, exclusive-or, complement and rotate (right, left, or nibble swap). The A-register is the accumulator, the B-register is dedicated during multiply and divide and serves as both a source and a destination. During all other operations the B-register is simply another location of the special function register space and may be used for any purpose.
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Boolean Processor The Boolean processor is an integral part of the processor architecture. It is an independent bit processor with its own instruction set, its own accumulator (the carry flag) and its own bit- addressable RAM and I/O. The bit manipulation instructions allow the direct addressing of 128 bits within the internal data RAM and several bits within the special function registers. The special function registers which have addresses exactly divisible by eight contain directly addressable bits. The Boolean processor can perform, on any addressable bit, the bit operations of set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set then-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag it can perform the bit operation of logical AND or logical OR with the result returned to the carry flag. Program Status Word Register (PSW) The PSW-flags record processor status information and control the operation of the processor. The carry (CY), auxiliary carry (AC), two user flags (F0 and F1), register bank select (RS0 and RS1), overflow (OV) and parity (P) flags reside in the program status word register. These flags are bit-memory-mapped within the byte-memory-mapped PSW. The CY, AC, and OV flags generally reflect the status of the latest arithmetic operations. The CY-flag is also the Boolean accumulator for bit operations. The P-flag always reflects the parity of the A-register. F0 and F1 are general purpose flags which are pushed onto the stack as part of a PSW-save. The two register bank select bits (RS1 and RS0) determine which one of the four register banks is selected as follows: Table 6 Program Status Word Register RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 Register Location 00H - 07H 08H - 0FH 10H - 17H 18H - 1FH
Program Status Word PSW Program Status Word (MSB) CY AC F0 RS1 RS0 OV F1 PSW SFR-Address D0H (LSB) P
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Stack Pointer (SP) The 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. This is also the address of the next byte that will be popped. The SP is incremented during a push. SP can be read or written to under software control. The stack may be located anywhere within the internal data RAM address space and may be as large as 256 bytes. Data Pointer Register (DPTR) The 16-bit Data Pointer Register DPTR is the concatenation of registers DPH (highorder byte) and DPL (low-order byte). The DPTR is used in register-indirect addressing to move program memory constants and to access the extended data memory. DPTR may be manipulated as one 16-bit register or as two independent 8-bit registers DPL and DPH. Eight data pointer registers are available, the active one is selected by a special function register (DPSEL). Port 0, Port 1, Port 2, Port 3, Port 4 The five ports provide 26 I/O-lines and 5 input-lines to interface to the external world. All five ports are both byte and bit addressable. Port 0 is used for binary l/O and as clock and data line of a software driven I2C bus. Port 1 provides eight PWM- output channels as alternate functions while port 2.0 - 2.3 are digital or analog inputs. Port 3 contains special control signals. Port 4 will usually be selected as memory extension interface (ROM-less version only). Interrupt Logic Controlled by three special function registers (IE, IP0 and IP1) the interrupt logic provides several interrupt vectors. Each of them may be assigned to high or low priority (see Chapter "Interrupt System" on page 62). Timer/Counter 0/1 Two general purpose 16-bit timers/counters are controlled by the special function registers TMOD and TCON (see Chapter "General Purpose Timers/Counters" on page 80). Serial Interface A full duplex serial interface is provided where one of three operation modes may be selected. The serial interface is controlled by two special function registers (SCON, SBUF) as described in Chapter "Serial Interface" on page 91.
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Watchdog Timer For software- and hardware security, a watchdog timer is supplied, which resets the processor, if not cleared by software within a maximum time period. Pulse Width Modulation Unit Up to six lines of port 1 may be used as 8-bit PWM-outputs and two lines of port 1 may be used as 14-bit PWM-output. The PWM-logic is controlled by registers PWCOMP0 ... 7, PWCL, PWCH, PWME, PWEXT6, PWEXT7 (see Chapter "Pulse Width Modulation Unit (PWM)" on page 106). Capture Compare Timer For easy decoding of infrared remote control signals, a dedicated timer is available (see Chapter "Capture Compare Timer" on page 90). 6.3.1.2 CPU-Timing
Timing generation is completely self-contained, except for the frequency reference which can be a crystal or external clock source. The on-board oscillator is a parallel antiresonant circuit. There is a divide-by-6 internal timing which leads to a minimum instruction cycle of 0.33 s with an 18-MHz crystal. The XTAL2-pin is the output of a high-gain amplifier, while XTAL1 is its input. A crystal connected between XTAL1 and XTAL2 provides the feedback and phase shift required for oscillation. A machine cycle consists of 6 oscillator periods (software selectable). Most instructions execute in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete. They take four cycles. To reduce the power consumption, the internal clock frequency can be divided by two, which slows down the processor operations. This slow down mode is entered by setting SFR-Bit CDC in register AFR.
Note: All timing values and diagrams in this specification refer to an inactivated clock divider (CDC = 0). Note: Slow down mode should only be used if teletext reception and the display are disabled. Otherwise processing of the incoming text data might be incomplete and the display structure will be corrupted.
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.2 . OSC
CDC = 1 Internal Chip Clock CDC = 0 .6 . Machine Cycles, Instruction Cycles
UES05470
Figure 14 CPU-Timing
Note: For CDC see Chapter "Advanced Function Register" on page 115.
6.3.1.3 Addressing Modes
There are five general addressing modes operating on bytes. One of these five addressing modes, however, operates on both bytes and bits: - - - - - Register Direct (both bytes and bits) Register indirect Immediate Base-register plus index-register indirect
The following section summarizes, which memory spaces may be accessed by each of the addressing modes: Register Addressing R0 - R7 ACC, B, CY (bit), DPTR Direct Addressing RAM (low part) Special Function Registers Register-Indirect Addressing RAM (@R1, @R0, SP) Immediate Addressing Program Memory Base-Register plus Index-Register Indirect Addressing Program Memory (@DPTR + A, @PC + A)
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Register Addressing Register addressing accesses the eight working registers (R0 - R7) of the selected register bank. The PSW-register flags RS1 and RS0 determine which register bank is enabled. The least significant three bits of the instruction opcode indicate which register is to be used. ACC, B, DPTR and CY, the Boolean processor accumulator, can also be addressed as registers. Direct Addressing Direct byte addressing specifies an on-chip RAM-location (only low part) or a special function register. Direct addressing is the only method of accessing the special function registers. An additional byte is appended to the instruction opcode to provide the memory location address. The highest-order bit of this byte selects one of two groups of addresses: values between 0 and 127 (00H - 7FH) access internal RAM-locations, while values between 128 and 255 (80H - 0FFH) access one of the special function registers. Register-Indirect Addressing Register-indirect addressing uses the contents of either R0 or R1 (in the selected register bank) as a pointer to locations in the 256 bytes of internal RAM. Note that the special function registers are not accessable by this method. Execution of PUSH- and POP-instructions also use register-indirect addressing. The stack pointer may reside anywhere in internal RAM. Immediate Addressing Immediate addressing allows constants to be part of the opcode instruction in program memory. An additional byte is appended to the instruction to hold the source variable. In the assembly language and instruction set, a number sign (#) precedes the value to be used, which may refer to a constant, an expression, or a symbolic name. Base-Register plus Index Register-Indirect Addressing Base-register plus index register-indirect addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (DPTR or PC) and index register, ACC. This mode facilitates accessing to look-up-table resident in program memory.
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6.3.2
Memory Organization
The processor memory is organized into two address spaces. The memory spaces are: - Program memory address space - 256 byte plus 128-byte internal data memory address space - Extended internal data memory (XRAM) for storing teletext and display data. A 16-bit program counter and a dedicated banking logic provide the processor with its 512-Kbyte addressing capabilities (for ROM-less versions, up to 19 address lines are available). The program counter allows the user to execute calls and branches to any location within the program memory space. There are no instructions that permit program execution to move from the program memory space to any of the data memory space. 6.3.2.1 Program Memory
Certain locations in program memory are reserved for specific programs. Locations 0000 through 0002 are reserved for the initialization program. Following reset, the CPU always begins execution at location 0000. Locations 0003 through 0051 are reserved for the seven interrupt-request service programs as indicated in Table 7. Table 7 Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Interface Teletext Sync Signals Analog Digital Converter Address 03 11 19 27 35 43 51 (03H) (0BH) (13H) (1BH) (23H) (2BH) (33H)
Depending on the selected type, the user can access a part of the internal/external ROM for the application software. Please note that another part of the Program Memory is reserved for the TTX firmware. Table 8 Type SDA 5250 SDA 5251 SDA 5252 SDA 5254 SDA 5255 Available User ROM Space 480 8 16 16 24 Kbyte Kbyte Kbyte Kbyte Kbyte externally internally internally internally internally
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Memory Extension (ROMless version only) The processor is prepared to extend its external program memory space up to 512 Kbytes (Figure 15 and 16). For easy handling of existing software and assemblers this space is split into 8 banks of 64 Kbytes each. The extension concept, based on the standard 64 K addressing ability, is provided for high effective and easy memory access with minimum software overhead. There is also no need caring about bank organization during subroutine processing or interrupts. This is done through address bits A16 - 18, which are controlled by a special internal circuitry, performing a "delayed banking". The operations to the extended memory spaces are controlled by two additional special function registers called MEX1 and MEX2 (Figure 17). The address bits A17 and A18 are implemented at port 4. Programs, using only 128-Kbytes program memory space, may switch the address function off by setting bits NB, IB and bits MB to `1' followed by a LJMP. Then port 4 will work properly in port mode. Whenever full address mode is desired, port 4 bits have to be kept on `1' (Table 9). After reset all CB are `0' and P4 latches are set to `1', resulting a `0' at the port 4 pins. Banking of Program Memory After reset the bits for current bank (CB) and next bank (NB) are set to zero. This way the processor starts the same as any 8051 controller at address 00000H. Whenever a jump to another bank is required, the software has to change the bits NB16 - 18 for initializing the bank exchange (bits CB16 - 18 are read only). After operating the next LJMP instruction the NB16 - 18 bits (next bank) are copied to CB16 - 18 (current bank) and will appear at A16 - 18. Only LJMP will do this.
P0 P1 D D EPROM
SDA 5250
P2 P3 P4 A PSEN A
OE Alternative Connections
UES05663
Figure 15 Connecting External Program Memory
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524287 458751 393215 327679 262143 196607 131071 65535 2 1 Bank 0 0000 3 4 5 6 7 458752 393216 327680 262144 196608 131072 65536
UEC04716
Figure 16 Bank Organization
MEX1 (94H): 7 - 6
Bank Control 5 CB17 4 CB16 3 - 2 NB18 1 NB17 0 NB16
CB18
MEX2 (95H): 7 MM CB NB MM MB SF IB 6
Mode Control 5 MB17 4 MB16 3 SF 2 IB18 1 IB17 0 IB16
MB18
= Current Bank = Next Bank = Memory Mode = Memory Bank = Stack Full = Interrupt Bank
Read only; CBx = Ax R/W R/W; 1 = use MB R/W Read only; 1 = full R/W
Figure 17 Register Bits MEX1 / MEX2
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Table 9 Port 4 Configuration CB 0 0 1 1 MOVC-Handling MOVC-instructions may operate in two different modes, that are selected by bit MM in MEX2. On MM = 0 MOVC will access the current bank. On MM = 1 the bits MB16 - 18 will appear at A16 - A18 during MOVC. P4 Latch 0 1 0 1 P4 Out 0 0 0 1 Comment x Address P4 Addr / P4
Bank 3 Bank 2
DPTR PC MM=1, MB16-17 =3, CB 16-17 =2
UEC04717
Figure 18 PC and DPTR on Different Banks CALLs and Interrupts For flexible use of CALL and interrupts the control logic holds an own 32 levels-six-bitstack. Whenever a LCALL or ACALL occurs, CB16 - 18 and NB16 - 18 (MEX1) is copied to this stack and the memory extension stackpointer is incremented. Then NB16 - 18 is copied to CB16 - 18. Leaving subroutines through RET or RETI decrements the stack pointer and reads the old NB and CB contents from the stack. All six bits are required for saving to prevent conflicts on interrupt events. One additional feature simplifies the handling of interrupts: on occurrence the bits IB16 - 18 within MEX2 are copied to CB16 - 18 and NB16 - 18 after pushing their old contents on the stack. This way programmers can place their ISR (Interrupt Service Routine) on specific banks. After reset MM, MB16 - 18 and IB16 - 18 are set to zero.
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In order to prevent loss of program control during deep subroutine nesting a warning bit "SF" (Stack Full) is set in MEX2 whenever a memory extension stack depth overflow is imminent. For example Figure 19 shows the data flows at the memory extension stack during a LCALL. All three bits of NB are copied to the position CB and NB of the next higher stack level (now the current MEX1) while the last CB and NB are held on the stack. Returning from subroutine through RET the memory extension stack pointer decrements and CB and NB of MEX1 has the same contents as before LCALL.
Before CB NB
'LCALL'
After CB NB
MEX1 MEX1 010 110 010 110
110 010
110 110
MEX1:
CB 18,17,16
NB 18,17,16
UEC04718
Figure 19 Processing LCALL (same as ACALL) Examples The standard sequence jumping from one bank to another is simply preceding a "MOV MEX1,#"- instruction to an "LJMP / LCALL" as shown in Figure 19. To operate programs up to 512 Kbytes with standard assemblers or from C the program can be split into sections, modules or files, that will each run in their own bank. Referencing banks to each other (jumps, calls, data moves) may be done by a simple preprocessing of the source programs or object files. Users, going to program a 512-Kbyte EPROM in assembler, may proceed like this: 1. Build up to eight assembler source files (max. 64 K), inter bank operations will refer to dummy labels. 2. Do assembler runs on each block and generate label lists. 3. Preprocessing: substitute the inter bank labels in the source files with absolute 64 K addresses. 4. Second and final assembler runs on each block, generate Hex files. 5. Append the Hex files in right order. 6. Program an EPROM.
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More comfortable programming, e. g. based on C-programs, require similar processing of the source programs or object files with respect to special considerations of the compiler. Figure 20 shows an assembler program run, performing the following actions: 1. Start at bank 0 at 00000. 2. Set ISR-page to bank 2. 3. Jump to bank 1 at address 25. 4. Being interrupted to bank 2 ISR. 5. Call a subprogram at bank 2 address 43. 6. After return read data from bank 2.
Bank 2 Bank 1 Bank 0 ORG 25 ORG 40 ;set ISR Bank = Bank 2 0040: PRGM0: MOV MEX2,#02 ;Prepare jumping ;from ;Bank 0 to Bank 1 0043: 0046: MOV MEX1,#1 LJMP 25 ;'25' is a substitution of Primary Labels transformed to an Absolute Address at Bank 2 ;Fetch Data from Bank 2 ;(and update ISR-Bank pointer) 0150: 0153: 0156: MOV MEX2,#0A2 H MOV DPTR,#100 MOVC A, @DPTR 0040: 0080: 0025: PRGM1: MOV... ;Prepare ;Calling PRGM2 ;on Bank 2 MOV MEX1,#2 LCALL 43 Interrupt RETI ORG 43 0043: 0060: PRGM2: ;Execute PRGM2 RET ORG 100 0100: BYTE 44 H 0013: ;ISR on ;Bank 2 ORG 13
to AKKU
UEC04719
Figure 20 Program Example
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6.3.2.2
Internal Data RAM
The internal data memory is divided into four blocks: the lower 128 byte of RAM, the upper 128 byte of RAM, the 128-byte Special Function Register (SFR) area and the up to 10 Kbyte additional RAM (Figure 21). Because the upper RAM-area and the SFRarea share the same address locations, they are accessed through different addressing modes. The internal data RAM-address space is 0 to 255. Four banks of eight registers each occupy locations 0 through 31. Only one of these banks may be enabled at a time through a two-bit field in the PSW. In addition, 128-bit locations of the on-chip RAM are accessible through direct addressing. These bits reside in internal data RAM at byte locations 32 through 47, as shown in Table 11. The lower 128 bytes of internal data RAM can be accessed through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through registerindirect addressing and the special function registers through direct addressing.The stack can be located anywhere in the internal data RAM-address space. The stack depth is limited only by the available internal data RAM, thanks to an 8-bit relocatable stack pointer. The stack is used for storing the program counter during subroutine calls and may also be used for passing parameters. Any byte of internal data RAM or special function registers accessible through direct addressing can be pushed/popped. An additional on-chip RAM-space called "XRAM" extends the internal RAM-capacity. The up to 10 Kbytes of XRAM are accessed by MOVX @DPTR. XRAM is located in the upper area of the address space. 1 Kbyte of the XRAM, called VBI Buffer, is reserved for storing teletext data and another up to 8 Kbyte of the XRAM, called Display Chapters, are reserved for storing up to 8 display chapters (see Figure 21). Unused memory area of the VBI Buffer and the Display Chapters can be used by the controller as general RAM space.
:
Table 10 XRAM Address Space Function VBI Buffer Display Chapter 0 - 7 CPU XRAM
(1) (2)
Byte Address (hex.) F400 - F7FF C000 - DFFF(1) F800 - FBFF(2)
SDA 5251, SDA 5252 C000 - C3FF only SDA 5250, SDA 5254 and SDA 5255 only
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6.3.2.3
Special Function Registers
The special function register address space resides between addresses 128 and 255. All registers except the program counter and the four banks of eight working registers reside here. Memory mapping the special function registers allows them to be accessed as easily as the internal RAM. As such, they can be operated on by most instructions. A complete list of the special function registers is given in Table 13. In addition, many bit locations within the special function register address space can be accessed using direct addressing. These direct addressable bits are located at byte addresses divisible by eight as shown in Table 12.
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255
255
64511 63488 63487 62464 57343 56320 56319 55296 55295
Controller Work Space VBI Buffer Display Chapter 7 Display Chapter 6 Display Chapter 5 Display Chapter 4 Display Chapter 3 Display Chapter 2 Display Chapter 1 Display Chapter 0
UED05467
Internal DATA RAM
Special Function Registers
Addressable Bits in SFRs
128 127
128
Addressable Bits in RAM (128 Bits)
48 47 32 31 24
127 7 R7 R0 R7
120 0 BANK 3 Internal DATA RAM 54272 54271 53248 53247 52224 52223 51200 51199 50176 50175 49152
Additional Internal DATA RAM (XRAM)
BANK 2
Registers
16
R0 R7 BANK 1
8
R0 R7 BANK 0
0
R0
SDA 5250, SDA 5254 and SDA 5255 only
Figure 21 Internal Data Memory Address Space
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Table 11 Internal RAM-Bit Addresses
RAM Byte 256
(MSB)
(LSB)
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Bank 3 24 23 Bank 2 16 15 Bank 1 8 7 Bank 0 0 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
FFH
2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH 18H 17H 10H 0FH 08H 07H 00H
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Table 12 Special Function Register Bit Address Space
Direct Byte Address F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H FF F7 - E7 DF D7 - C7 - B7 AF - 9F 97 8F 87 FE F6 - E6 DE D6 CE C6 - B6 AE - 9E 96 8E 86 FD F5 - E5 DD D5 CD C5 - B5 AD - 9D 95 8D 85 Bit Address FC F4 - E4 DC D4 CC C4 - B4 AC - 9C 94 8C 84 FB F3 - E3 DB D3 CB C3 - B3 AB A3 9B 93 8B 83 FA F2 - E2 - D2 CA C2 - B2 AA A2 9A 92 8A 82 F9 F1 E9 E1 D9 D1 C9 C1 - B1 A9 A1 99 91 89 81 F8 F0 E8 E0 D8 D0 C8 C0 - B0 A8 A0 98 90 88 80 P3 IE P2 SCON P1 TCON P0 Hardware Register Symbol PWME B P4 ACC ADCON PSW TTXSIR ACQSIR
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Table 13 Special Function Register Overview
Special Function Register Description Symbolic Name Address Location (hex.) Address Location (dec.) Bit Address Initial MSB ... LSB Value after (hex.) Reset (hex./bin.) E7 - E0 F7 - F0 D7 - D0 - - - - 00 00 00 07 00 00 xxxxx000 000xxx00 FF FF FF FF xxxxxx00 00 00 00 xxxx0101 00 00 00 00 00 00 00 00 00 00 xx xx xx xx 00 1998-04-08
Arithmetic Registers Accumulator B-Register Program Status Word System Control Registers Stack Pointer Data Pointer (high byte) Data Pointer (low byte) Data Pointer Select Power Control I/O-Port Registers Port 0 Port 1 Port 2 Port 3 Port 4 Interrupt Control Registers Interrupt Enable Flags Interrupt Priority Flags Interrupt Priority Flags Interrupt Control Timer 0/1 Registers Timer 0/1 Mode Register Timer 0/1 Control Register Timer 1 (high byte) Timer 0 (high byte) Timer 1 (low byte) Timer 0 (low byte) Watchdog Timer Registers Watchdog Control Register Watchdog Reload Register Watchdog Low Byte Watchdog High Byte Capture Compare Timer Registers
ACC, A B PSW SP DPH DPL DPSEL PCON P0 P1 P2 P3 P4 IE IP0 IP1 IRCON TMOD TCON TH1 TH0 TL1 TL0 WDCON WDTREL WDTL WDTH RELL RELH CAPL CAPH IRTCON
E0 F0 D0 81 83 82 A2 87 80 90 A0 B0 E8 A8 A9 AA A8 89 88 8D 8C 8B 8A A7 86 84 85 E1 E2 E3 E4 E5 60
224 240 208 129 131 130 162 135 128 144 160 176 232 168 169 170 171 137 136 141 140 139 138 167 134 132 133 225 226 227 228 229
87 - 80 97 - 90 A3 - A0 B7 - B0 E9 - E8 AF - A8 - - - - 8F - 88 - - - - - - - - - - - - -
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Table 13 Special Function Register Overview (cont'd)
Special Function Register Description Symbolic Name Address Location (hex.) Address Location (dec.) Bit Address Initial MSB ... LSB Value after (hex.) Reset (hex./bin.) DF - D8 - - 00 00 xx
Analog Digital Converter ADC-Control Register ADC-Data Register ADC-Start Register Pulse Width Modulator Registers Enable Register Counter Register (low byte) Counter Register (high byte) Compare Register 0 Compare Register 1 Compare Register 2 Compare Register 3 Compare Register 4 Compare Register 5 PWM 14 Compare Reg. 0 PWM 14 Extension Reg. 0 PWM 14 Compare Reg. 1 PWM 14 Extension Reg. 1 Serial Interface Registers Serial Control Register Serial Data Register Advanced Function Register Slicer Control Registers Acq. Sync Interrupt Register Acquisition Mode Register 1 Acquisition Mode Register 2
ADCON ADDAT DAPR
D8 D9 DA
216 217 218
PWME PWCL PWCH PWCOMP0 PWCOMP1 PWCOMP2 PWCOMP3 PWCOMP4 PWCOMP5 PWCOMP6 PWEXT6 PWCOMP7 PWEXT7 SCON SBUF AFR ACQSIR ACQMS_1 ACQMS_2
F8 F7 F9 F1 F2 F3 F4 F5 F6 FB FA FD FC 98 99 A6 C0 C1 C2
248 247 249 241 242 243 244 245 246 251 250 253 252 144 145 166 192 193 194
FF - F8 - - - - - - - - - - - - 9F - 98 - - C7 - C0 - -
00 00 00 FF FF FF FF FF FF FF FF FF FF 00 xx 00xxxxxx 00 00 00
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Table 13 Special Function Register Overview (cont'd)
Special Function Register Description Symbolic Name Address Location (hex.) Address Location (dec.) Bit Address Initial MSB ... LSB Value after (hex.) Reset (hex./bin.) - - - - - CF - C8 - - - - - - 00 00 00 00 00 00 00 00 00 00 00 x0
Display Control Registers Horizontal Delay Vertical Delay Transparent Control Mode 1 Register Mode 2 Register Sync Interrupt Request Reg. Language Control Cursor Column Position Cursor Row Position Display Timing Control Sandcastle Control Display Mode
DHD DVD DTCR DMODE1 DMODE2 TTXSIR LANGC DCCP DCRP DTIM SCCON DMOD
C3 C4 C5 C6 C7 C8 C9 CA CB CC CE D6
195 196 197 198 199 200 201 202 203 204 206 214
6.3.3
Interrupt System
External events and the real-time on-chip peripherals require CPU-service asynchronous to the execution of any particular section of code. To couple the asynchronous activities of these functions to normal program execution, a sophisticated multiple-source, four-priority-level, nested interrupt system is provided. Interrupt response delay ranges from 0,89 s to 2.33 s when using an 18-MHz clock (see Chapter "Advanced Function Register" on page 115). 6.3.3.1 Interrupt Sources
The processor acknowledges interrupt requests from seven sources: two from external sources via the INT0 and INT1 pins, one from each of the two internal counters, one from the serial I/O-port, one from teletext sync signals and one from the analog digital converter. Each of the seven sources can be assigned to either of four priority levels and can be independently enabled and disabled. Additionally, all enabled sources can be globally disabled or enabled. Interrupts result in a transfer of control to a new program location. Each interrupt vectors to a separate location in program memory for its service program. The program servicing the request begins at this address. The starting address (interrupt vector) of the interrupt service program for each interrupt source is shown in the Table 14.
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Table 14 Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface Teletext Sync Signals Analog Digital Converter 6.3.4 Interrupt Control Starting Address 03 11 19 27 35 43 51 (03H) (0BH) (13H) (1BH) (23H) (2BH) (33H)
The information flags, which control the entire interrupt system, are stored in following special function registers: IE IP0 IP1 IRCON TCON SCON TTXSIR ACQSIR ADCON Interrupt Enable Register Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Control Timer/Counter Control Register Serial Control Register Sync Interrupt Request Register Acquisition Sync Interrupt Register ADC-Control Register A8H A9H AAH ABH 88H 98H C8H C0H D8H
The interrupt system is shown diagrammatically in Figure 23. A source requests an interrupt by setting its associated interrupt request flag in the TCON, SCON, TTXSIR, ACQSIR or ADCON- register, as described in detail in Table 15.
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Table 15 Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface Teletext Sync Signals Request Flag IE0 TF0 IE1 TF1 RI/TI DVIRST DHIRST EVENST LIN24ST AVIRST AHIRST IADC Bit Location TCON.1 TCON.5 TCON.3 TCON.7 SCON.0/.1 TTXSIR.2 TTXSIR.0 ACQSIR.6 ACQSIR.4 ACQSIR.2 ACQSIR.0 ADCON.5
Analog Digital Converter
The timer 0 and timer 1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective timer/counter register, except for timer 0 in mode 3. The serial interface interrupt (receive or transmit) is generated when flag RI or TI is set. RI or TI will be set, when a byte has been received or transmitted over the serial port. For details see Chapter "More about Mode 0" on page 95, Chapter "More about Mode 1" on page 95 and Chapter "More about Modes 2 and 3" on page 96. The teletext sync signal interrupt is generated by setting and enabling at least one of six possible signal sources: two signals from the display clock system (V and H) and 4 signals from the acquisition clock system (start of even field, start of ACQ- line 24 in each field, V and H) as shown in Figure 22. The teletext sync signal interrupt is synchronous to the respective acquisition or display clock system. Thus clock synchronous software timers can be realized. The analog digital converter interrupt is generated on completion of the analog digital conversion. Within the IE-register there are eight addressable flags. Seven flags enable/disable the seven interrupt sources when set/cleared. Setting/clearing the eighth flag permits a global enable/disable of all enabled interrupt requests. All the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupt requests can be cancelled by software.
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TTXSIR.2 Display V Display V Interrupt DVIRST TTXSIR.0 Display H Display H Interrupt DHIRST Start of EVEN FIELD ACQSIR.6 ACQ EVEN FIELD Interrupt EVENST ACQSIR.4 ACQ Line 24 Interrupt LIN24ST ACQSIR.2 ACQ V ACQ V Interrupt AVIRST ACQSIR.0 ACQ H ACQ H Interrupt AHIRST
TTXSIR.3
DVIREN TTXSIR.1
DHIREN ACQSIR.7 Teletext Sync Signal Interrupt TSI
EVENEN ACQSIR.5
_ <
Start of ACQ Line 24 (each field)
LIN24EN ACQSIR.3
AVIREN ACQSIR.1
AHIREN
UES05463
Figure 22 Teletext Sync Signal Interrupt System
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Input Level and Interrupt Request Flag Registers: TCON.1 INT 0 External Interrupt RQST 0 IE 0 TCON.5 Internal Timer 0 TF 0 TCON.3 INT 1 External Interrupt RQST 1 IE 1 TCON.7 Internal Timer 1 TF 1 SCON 1/0 Internal Serial Port RI/TI ICCON.4 Internal 2 C IIN ADCON.5 Internal Analog Digital Converter IADC
Interrupt ENABLE Register: Source ENABLE IE.0 Global ENABLE IE.7 IP1.0
Interrupt Priority Registers: Highest Priority Level
IP0.0
EX 0 IE.1 IP1.1 IP0.1
Lowest Priority Level
ET 0 IE.2 IP1.2 IP0.2
EX 1
Priority Sequence
UES05465
IE.3
IP1.3
IP0.3
ET 1 IE.4 IP1.4 IP0.4
ES IE.5 IP1.5 IP0.5
EIC IE.6
EA IP1.6 IP0.6
EAD
EA
* * * * * * *
SEVEN INTERRUPT SOURCES EACH INTERRUPT CAN BE INDIVIDUALLY ENABLED/DISABLED ENABLED INTERRUPTS CAN BE GLOBALLY ENABLED/DISABLED EACH INTERRUPT CAN BE ASSIGNED TO EITHER OF FOUR PRIORITY LEVELS EACH INTERRUPT VECTORS TO A SEPARATE LOCATION IN PROGRAM MEMORY INTERRUPT NESTING TO FOUR LEVELS EXTERNAL INTERRUPT REQUESTS CAN BE PROGRAMMED TO BE LEVEL- OR TRANSITION-ACTIVATED
Figure 23 Interrupt System
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Teletext Sync Interrupt Request Register TTXSIR Teletext Sync Interrupt Request Register Default after reset: 00H (MSB) - VSY HSY PCLK DVIREN DVIRST DHIREN (LSB) DHIRST TTXSIR SFR-Address C8H
VSY, HSY, PCLK
These bits are no interrupt bits. They are described in Chapter "Display Special Function Registers" on page 24. Enables or disables the display vertical sync interrupt request. If DVIREN = 1, this interrupt will be enabled. Display vertical sync interrupt request flag. Set by the rising edge of the display vertical sync pulse. Must be cleared by software. Enables or disables the display horizontal sync interrupt request. If DHIREN = 1, this interrupt will be enabled. Display horizontal sync interrupt request flag. Set by the rising edge of the display horizontal sync pulse. Must be cleared by software.
DVIREN DVIRST
DHIREN
DHIRST
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Acquisition Sync Interrupt Request Register ACQSIR Acquisition Sync Interrupt Request Register Default after reset: 00H (MSB) EVENEN EVENST LIN24EN LIN24ST AVIREN AVIRST AHIREN (LSB) AHIRST ACQSIR SFR-Address C0H
EVENEN EVENST
Enables or disables the even field interrupt request. If EVENEN = 1, this interrupt will be enabled. Even field interrupt request flag. Set at the start of even field (field 1). Must be cleared by software. Enables or disables the acquisition line 24 interrupt request. If LIN24EN = 1, this interrupt will be enabled. Acquisition line 24 interrupt request flag. Set at the start of acquisition line 24 in each field. Must be cleared by software. Enables or disables the acquisition vertical sync interrupt request. If AVIREN = 1, this interrupt will be enabled. Acquisition vertical sync interrupt request flag. Set by the rising edge of the acquisition vertical sync pulse. Must be cleared by software. Enables or disables the acquisition horizontal sync interrupt request. If AHIREN = 1, this interrupt will be enabled. Acquisition horizontal sync interrupt request flag. Set by the rising edge of the acquisition horizontal sync pulse. Must be cleared by software.
LIN24EN LIN24ST AVIREN
AVIRST
AHIREN
AHIRST
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Interrupt Enable Register IE Interrupt Enable Register Default after reset: 00H (MSB) EA EADC ETSI ES ET1 EX1 ET0 (LSB) EX0 IE SFR-Address A8H
EA
Enables or disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Enables or disables the analog digital converter interrupt. If EADC = 1, this interrupt will be enabled. Enables or disables the teletext sync interrupts. If ETSI = 1, this interrupt will be enabled. Enables or disables the serial interface interrupt. If ES = 1, this interrupt will be enabled. Enables or disables the timer 1 overflow interrupt. If ET1 = 1, the timer 1 interrupt will be enabled. Enables or disables external interrupt 1. If EX1 = 1, external interrupt 1 will be enabled. Enables or disables the timer 0 overflow interrupt. If ET0 = 1, the timer 0 interrupt will be enabled. Enables or disables external interrupt 0. If EX0 = 1, external interrupt 0 will be enabled.
EADC ETSI ES ET1 EX1 ET0 EX0
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Interrupt Priority Register IP0 and IP1 Interrupt Priority Register Default after reset: 00H (MSB) - IP0.6 IP0.5 IP0.4 IP1 IP0.3 IP0.2 IP0.1 (LSB) IP0.0 IP0 SFR-Address A9H
Interrupt Priority Register Default after reset: 00H (MSB) - IP1.6 IP1.5 IP1.4
SFR-Address AAH (LSB) IP1.3 IP1.2 IP1.1 IP1.0
Corresponding bit-locations in both registers are used to set the interrupt priority level of an interrupt. Table 16 IP1.X 0 0 1 1 Table 17 Bit IP1.0 / IP0.0 IP1.1 / IP0.1 IP1.2 / IP0.2 IP1.3 / IP0.3 IP1.4 / IP0.4 IP1.5 / IP0.5 IP1.6 / IP0.6 Corresponding Interrupt IE0 TF0 IE1 TF1 RI/TI DVIRST/ DHIRST/ EVENST/ LIN24ST/AVIRST/AHIRST IADC IP0.X 0 1 0 1 Function Set priority level 0 (lowest) Set priority level 1 Set priority level 2 Set priority level 3 (highest)
Setting/clearing a bit in the IP-registers establishes its associated interrupt request priority level. If a low-priority level interrupt is being serviced, a higher-priority level interrupt will interrupt it. However, an interrupt source cannot interrupt a service program of the same or higher priority level.
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If two requests of different priority levels are received simultaneously, the request of higher priority level will be serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, see in Table 18. Table 18 Source 1. 2. 3. 4. 5. 6. IE0 TF0 IE1 TF1 RI/TI DVIRST DHIRST EVENST LIN24ST AVIRST AHIRST IADC Priority within Level (highest)
7.
(lowest)
Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level. 6.3.4.1 Interrupt Nesting
The process whereby a higher-level interrupt request interrupts a lower-level interrupt service program is called nesting. In this case the address of the next instruction in the lower-priority service program is pushed onto the stack, the stack pointer is incremented by two and processor control is transferred to the program memory location of the first instruction of the higher-level service program. The last instruction of the higher-priority interrupt service program must be a RETI-instruction. This instruction clears the higher "priority-level-active" flip-flop. RETI also returns processor control to the next instruction of the lower-level interrupt service program. Since the lower "priority-level-active" flipflop has remained set, higher priority interrupts are re-enabled while further lower-priority interrupts remain disabled.
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6.3.4.2
External Interrupts
The external interrupt request inputs (INT0 and INT1) can be programmed for either transition- activated or level-activated operation. Control of the external interrupts is provided by the four low- order bits of TCON as shown in the follow section. When IT0 and IT1 are set to one, interrupt requests on INT0 and INT1 are transitionactivated (high-to-low), else they are low-level activated. IE0 and IE1 are the interrupt request flags. These flags are set when their corresponding interrupt request inputs at INT0 and INT1, respectively, are low when sampled by the processor and the transitionactivated scheme is selected by IT0 and IT1. Function of Lower Nibble Bits in TCON Timer and Interrupt Control Register Default after reset: 00H (MSB) TF1 TR1 TF0 TR0 IE1 IT1 IE0 (LSB) IT0 TCON SFR-Address 88H
TCON.4 - TCON.7 IE1 IT1
See Chapter "General Purpose Timers/Counters" on page 80. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. IT1 = 1 selects transition-activated external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. IT0 = 1 selects transition-activated external interrupts.
IE0 IT0
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Interrupt Control Register Default after reset: XXXX0101B (MSB) - - - -
IRCON
SFR-Address ABH (LSB)
EX1R
EX1F
EX0R
EX0F
EX1R EX1F EX0R EX0F
if set, EX1-interrupt detection on rising edge at Pin P3.3 if set, EX1-interrupt detection on falling edge at Pin P3.3 if set, EX0-interrupt detection on rising edge at Pin P3.2 if set, EX0-interrupt detection on falling edge at Pin P3.2
- Transition-Activated Interrupts (IT0 = 1, IT1 = 1) The IE0, IE1 flags are set by a transition at INT0, INT1, respectively; they are cleared during entering the corresponding interrupt service routine. For transition-activated operation, the input must remain active for more than six oscillator periods, but needs not to be synchronous with the oscillator. The opposite transition of a transition-activated input may occur at any time after the six oscillator period latching time, but the input must remain inactive for six oscillator periods before reactivation. - Level-Activated Interrupts (IT0 = 0, IT1 = 0) The IE0, IE1 flags are set whenever INT0, INT1 are respectively sampled at low level. Sampling INT0, INT1 at high level clears IE0, IE1, respectively. For level-activated operation, if the input is active during the sampling that occurs seven oscillator periods before the end of the instruction in progress, an interrupt subroutine call is made. The level-activated input needs to be low only during the sampling that occurs seven oscillator periods before the end of the instruction in progress and may remain low during the entire execution of the service program. However, the input must be deactivated before the service routine is completed to avoid invoking a second interrupt, or else another interrupt will be generated. Extension of Standard 8051 Interrupt Logic For more flexibility, the SDA 525x family provides a new feature in detection EX0 and EX1 in edge-triggered mode. Now there is the possibility to trigger an interrupt on the falling and / or rising edge at the dedicated Port3-Pin. Therefore, an additional register IRCON has been defined, which is described on the top.
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6.3.4.3
Interrupt Task Function
The processor records the active priority level(s) by setting internal flip-flop(s). Each interrupt level has its own flip-flop. The flip-flop corresponding to the interrupt level being serviced is reset when the processor executes a RETI-instruction. The sequence of events for an interrupt is: - A source provokes an interrupt by setting its associated interrupt request bit to let the processor know an interrupt condition has occurred. - The interrupt request is conditioned by bits in the interrupt enable and interrupt priority registers. - The processor acknowledges the interrupt by setting one of the four internal "prioritylevel active" flip-flops and performing a hardware subroutine call. This call pushes the PC (but not the PSW) onto the stack and, for some sources, clears the interrupt request flag. - The service program is executed. - Control is returned to the main program when the RETI-instruction is executed. The RETI- instruction also clears one of the internal "priority-level active" flip-flops. The interrupt request flags IE0, IE1, TF0 and TF1 are cleared when the processor transfers control to the first instruction of the interrupt service program. The RI/TI, DVIRST, DHIRST, EVENST, LIN24ST, AVIRST, AHIRST and IADC-interrupt request flags must be cleared as part of the respective interrupt service program. 6.3.4.4 Response Time
The highest-priority interrupt request gets serviced at the end of the instruction in progress unless the request is made in the last seven (CDC=0) oscillator periods of the instruction in progress. Under this circumstance, the next instruction will also execute before the interrupt's subroutine call is made. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or IP0 and IP1, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a singleinterrupt system, the response time is always more than 3 cycles and less than 8 cycles (approximately 2.33 s at 18-MHz operation). Note, that a machine cycle can consist of 12 oscillator periods (CDC = 1) or only six oscillator periods (CDC = 0) (see Chapter "Advanced Function Register" on page 115). Examples of the best and worst case conditions are illustrated in Table 19.
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Table 19 Instruction Time (Oscillator Periods) Best Case External interrupt generated immediately 2+ before (best) / after (worst) the pin is sampled (time until end of bus cycle). Current or next instruction finishes in 12-[6-] oscillator periods Next instruction is MUL or DIV Internal latency for hardware subroutine call 12 [1 + ] Worst Case 2- [1 - ]
[6]
12
[6]
don't care 24 38 [12] [19]
48 24 86
[24] [12] [43]
Note: values without brackets apply for CDC = 1 and values in brackets for CDC = 0 (see Chapter "Advanced Function Register" on page 115). If an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. 6.3.5 Processor Reset and Initialization
Processor initialization is accomplished with activation of the RST pin, which is the input to a Schmitt Trigger. To reset the processor, this pin should be held low for at least four machine cycles, while the oscillator is running stable. Upon powering up, RST should be held low for at least 10 ms after the power supply stabilizes to allow the oscillator to stabilize. Crystal operation below 6 MHz will increase the time necessary to hold RST low. Two machine cycles after receiving of RST, the processor ceases from instruction execution and remains dormant for the duration of the pulse. The high-going transition then initiates a sequence which requires approximately one machine cycle to execute before normal operation commences with the instruction at absolute location 0000H. Program memory locations 0000H through 0002H are reserved for the initialization routine of the microcomputer. This sequence ends with registers initialized as shown in Chapter "Memory Organization" on page 49. After the processor is reset, all ports are written with one (1). Outputs are undefined until the reset period is complete. An automatic reset can be obtained when VDD is turned on by connecting the RST-pin to VSS through a 10 F capacitor, providing the VDD rise time does not exceed a millisecond and the oscillator start-up time does not exceed 10 milliseconds. When power comes on, the current drawn by RST-pin starts to charge the capacitor. The voltage VRST at RST-pin is the capacitor voltage, and increases to VDD as the capacitor charges. The larger the
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capacitor, the more slowly VRST decreases. VRST must remain below the lower threshold of the Schmitt Trigger long enough to effect a complete reset. The time required is the oscillator start-up time plus 4 machine cycles. Attention: While reset is active and at least four machine cycles after rising edge of RST, ALE, P4.0 and P3.6 should not be pulled down externally. Otherwise a special production test mode is entered.
VDD
VDD
RST
VRST VSS
10 F
VSS
UES04722
Figure 24 Power-On Reset Circuit Power-Down Operations The controller provides two modes in which power consumption can be significantly reduced. - Idle mode. The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. - Power-down mode. Operation of the controller is turned off. This mode is used to save the contents of internal RAM with a very low standby current. Both modes are entered by software. Special function register PCON is used to enter one of these modes.
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Power Control Register PCON Power Control Register Default after reset: 000xxx00 (MSB) SMOD PDS IDLS - - - PDE (LSB) IDLE PCON SFR-Address 87H
PDS IDLS PDE IDLE SMOD
Power-down start bit. The instruction that sets the PDS-flag is the last instruction before entering the power down mode. IDLE start bit. The instruction that sets the PDS-flag is the last instruction before entering the idle mode. Power-down enable bit. When set, starting the power-down mode is enabled. Idle enable bit. When set, starting the idle mode is enabled. Baud rate control for serial interface; if set, the baud rate is doubled.
Entering the idle mode is done by two consecutive instructions immediately following each other. The first instruction has to set bit IDLE (PCON.0) and must not set bit IDLS (PCON.5). The following instruction has to set bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). Bits IDLE and IDLS will automatically be cleared after having been set. This double-instruction sequence is implemented to minimize the chance of unintentionally entering the idle mode. The following instruction sequence may serve as an example: ORL ORL PCON,#00000001B PCON,#00100000B Set bit IDLE, bit IDLS must not be set. Set bit IDLS, bit IDLE must not be set.
The instruction that sets bit IDLS is the last instruction executed before going into idle mode. The idle mode can be terminated by activation of any enabled interrupt (or a hardware reset). The CPU-operation is resumed, the interrupt will be serviced and the next instruction to be executed after RETI-instruction will be the one following the instruction that set the bit IDLS. The port state and the contents of SFRs are held during idle mode. Entering the power-down mode is done by two consecutive instructions immediately following each other. The first instruction has to set bit PDE (PCON.1) and must not set bit PDS (PCON.6). The following instruction has to set bit PDS (PCON.6) and must not set bit PDE (PCON.1). Bits PDE and PDS will automatically be cleared after having been set. This double-instruction sequence is implemented to minimize the chance of
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unintentionally entering the power-down mode. The following instruction sequence may serve as an example: ORL ORL PCON,#00000010B PCON,#01000000B Set bit PDE, bit PDS must not be set. Set bit PDS, bit PDE must not be set.
The instruction that sets bit PDS is the last instruction executed before going into powerdown mode. If idle mode and power-down mode are invoked simultaneously, the power-down mode takes precedence. The only exit from power-down mode is a hardware reset. The reset will redefine all SFRs, but will not change the contents of internal RAM. 6.3.6 Ports and I/O-Pins
There are 26 I/O-pins configured as three 8-bit ports, one 4-bit-port (P2.0 - 2.3) and one 2-bit port (P4.0 - 4.1, P4.1 for ROM-less version only). Each pin can be individually and independently programmed as input or output and each can be configured dynamically. An instruction that uses a port's bit/byte as a source operand reads a value that is the logical AND of the last value written to the bit/byte and the polarity being applied to the pin/pins by an external device (this assumes that none of the processor's electrical specifications are being violated). An instruction that reads a bit/byte, operates on the content, and writes the result back to the bit/byte, reads the last value written to the bit/byte instead of the logic level at the pin/pins. Pins comprising a single port can be made a mixed collection of inputs and outputs by writing a "one" to each pin that is to be an input. Each time an instruction uses a port as the destination, the operation must write "ones" to those bits that correspond to the input pins. An input to a port pin needs not to be synchronized to the oscillator. All the port latches have "one" s written to them by the reset function. If a "zero" is subsequently written to a port latch, it can be reconfigured as an input by writing a "one" to it. The instructions that perform a read of, operation on, and write to a port's bit/byte are INC, DEC, CPL, JBC, SETB, CLR, MOV P.X, CJNE, DJNZ, ANL, ORL, and XRL. The source read by these operations is the last value that was written to the port, without regard to the levels being applied at the pins. This insures that bits written to a "one" (for use as inputs) are not inadvertently cleared. Port 0 has an open-drain output. Writing a "one" to the bit latch leaves the output transistor off, so the pin floats. In that condition it can be used as a high-impedance input. Port 0 is considered "true bidirectional", because when configured as an input it floats. Ports 1, 3 and 4 have "quasi-bidirectional" output drivers which comprise an internal pullup resistor of 10 k to 40 k. When configured as inputs they pull high and will
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source current when externally Characteristics" on page 129).
pulled
low
(for
details
see
Chapter "DC-
In ports P1, P3 and P4 the output drivers provide source current for one oscillator period if, and only if, software updates the bit in the output latch from a "zero" to an "one". Sourcing current only on "zero to one" transition prevents a pin, programmed as an input, from sourcing current into the external device that is driving the input pin. Secondary functions can be selected individually and independently for the pins of port 1 and 3. Further information on port 1's secondary functions is given in Chapter "Pulse Width Modulation Unit (PWM)" on page 106. P3 generates the secondary control signals automatically as long as the pin corresponding to the appropriate signal is programmed as an input, i. e. if the corresponding bit latch in the P3 special function register contains a "one". The following alternate functions can be selected when using the corresponding P3 pins: P3.0 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 ODD/EVEN INT0 INT1 T0 T1 RXD TXD (ODD/EVEN-indicator output) (external interrupt 0) (external interrupt 1) (Timer/Counter 0 external input) (Timer/Counter 1 external input) (serial port receive line) (serial port transmit line)
Read Modify-Write Feature "Read-modify-write" commands are instructions that read a value, possibly change it, and then rewrite it to the latch. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin. The read-modify-write instructions are listed in Table 20. The read-modify-write instructions are directed to the latch rather than the pin in order to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "one" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a 0. Reading the latch rather than the pin will return the correct value of "one".
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Table 20 Read-Modify-Write Instructions Mnemonic ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y, C(1) CLR PX.Y(1) SET PX.Y(1)
(1)
Description logical AND logical OR logical EX - OR jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit Y of Port X clear bit Y of Port X set bit Y of Port X
Example ANL P1, A ORL P2, A XRL P3, A JBC P1.1, LABEL CPL P3.0 INC P1 DEC P1 DJNZ P3, LABEL MOV P1.7, C CLR P2.6 SET P3.5
The instruction reads the port byte (all 8 bits), modifies the addressed bit, then writes the new byte back to the latch
6.3.7
General Purpose Timers/Counters
Two independent general purpose 16-bit timers/ counters are integrated for use in measuring time intervals, measuring pulse widths, counting events, and causing periodic (repetitive) interrupts. Either can be configured to operate as timer or event counter. In the "timer" function, the registers TLx and/or THx (x = 0, 1) are incremented once every machine cycle. Thus, one can think of it as counting machine cycles. A machine cycle consists of 6 or 12 oscillator periods. This depends on the setting of bit CDC in the Advanced Function Register AFR of the special function registers (see Chapter "Advanced Function Register" on page 115). For CDC = 1 a machine cycle consists of 12 oscillator periods and for CDC = 0 of 6 oscillator periods. In the "counter" function, the registers TLx and/or THx (x = 0, 1) are incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled during every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes 2 machine cycles (24 oscillator periods for CDC = 1 or 12 oscillator periods for CDC = 0) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency for CDC = 1 or 1/12 of the oscillator frequency for CDC = 0. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.
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Timer/Counter 0: Mode Selection Timer/counter 0 can be configured in one of four operating modes, which are selected by bit-pairs (M1, M0) in TMOD-register (see page 83). - Mode 0 Putting timer/counter 0 into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. Figure 25 shows the mode 0 operation as it applies to timer 0. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1 s to all 0 s, it sets the timer interrupt flag TF0. The counted input is enabled to the timer when TR0 = 1 and either GATE = 0 or INT0 = 1. (Setting GATE = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements.) TR0 is a control bit in the special function register TCON (see page 84). GATE is contained in register TMOD (see page 83). The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. - Mode 1 Mode 1 is the same as mode 0, except that the timer/counter 0 register is being run with all 16 bits. - Mode 2 Mode 2 configures the timer/counter 0 register as an 8-bit counter (TL0) with automatic reload, as shown on see page 83. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. - Mode 3 Timer/counter 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3 on timer 0 is shown in Figure 27. TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. With timer 0 in mode 3, the processor can operate as if it has three timers/counters. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used in any application not requiring an interrupt.
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Timer/Counter 1: Mode Selection Timer/counter 1 can also be configured in one of four modes, which are selected by its own bitpairs (M1, M0) in TMOD-register. The serial port receives a pulse each time that timer/counter 1 overflows. This pulse rate is divided to generate the transmission rate of the serial port. Modes 0 and 1 are the same as for counter 0. - Mode 2 The "reload" mode is reserved to determine the frequency of the serial clock signal (not implemented). - Mode 3 When counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables the increment counter. This mode is provided as an alternative to using the TR1 bit (in TCON-register) to start and stop timer/counter 1. Configuring the Timer/Counter Input The use of the timer/counter is determined by two 8-bit registers, TMOD (timer mode) and TCON (timer control), as shown on page 83 and 84. The input to the counter circuitry is from an external reference (for use as a counter), or from the on-chip oscillator (for use as a timer), depending on whether TMOD's C/T-bit is set or cleared, respectively. When used as a time base, the on-chip oscillator frequency is divided by twelve or six (see Figure 25, 26 and 26) before being used as the counter input. When TMOD's GATE bit is set (1), the external reference input (T1, T0) or the oscillator input is gated to the counter conditional upon a second external input (INT0), (INT1) being high. When the GATE bit is zero (0), the external reference, or oscillator input, is unconditionally enabled. In either case, the normal interrupt function of INT0 and INT1 is not affected by the counter's operation. If enabled, an interrupt will occur when the input at INT0 or INT1 is low. The counters are enabled for incrementing when TCON's TR1 and TR0 bits are set. When the counters overflow, the TF1 and TF0 bits in TCON get set, and interrupt requests are generated. The counter circuitry counts up to all 1's and then overflows to either 0's or the reload value. Upon overflow, TF1 or TF0 is set. When an instruction changes the timer's mode or alters its control bits, the actual change occurs at the end of the instruction's execution. The T1 and T0 inputs are sampled near the falling-edge of ALE in the tenth, twentysecond, thirty-fourth and forty-sixth oscillator periods of the instruction-in-progress (CDC=1). Thus, an external reference's high and low times must each have a minimum duration of twelve oscillator periods for CDC = 1 or six oscillator periods for CDC = 0. There is a twelve (CDC = 1) or six (CDC = 0) oscillator period delay from the time when a toggled input (transition from high to low) is sampled to the time when the counter is incremented.
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Timer/Counter Mode Register Timer 0/1 Mode Register Default after reset: 00H (MSB) GATE C/T Timer 1 GATE M1 M0 GATE C/T Timer 0 M1 (LSB) M0 TMOD SFR-Address 89H
Gating control when set. Timer/counter "x" is enabled only while "INTx" pin is high and "TRx" control bit is set. When cleared, timer "x" is enabled, whenever "TRx" control bit is set. Timer or counter selector. Cleared for timer operation (input from internal system clock). Set for Counter operation (input from "Tx" input pin).
C/T
Table 21 M1 0 0 1 1 M0 0 1 0 1 Operating Mode SAB 8048 timer: "TLx" serves as five-bit prescaler. 16-bit timer/counter: "THx" and "TLx" are cascaded, there is no prescaler. 8-bit auto-reload timer/counter: "THx" holds a value which is to be reloaded into "TLx" each time it overflows. (Timer 0) TL0 is an eight-bit timer/counter controlled by the standard timer 0 control bits; TH0 is an eight-bit timer only controlled by timer 1 control bits. (Timer 1) timer/counter 1 is stopped.
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Timer/Counter Control Register Timer 0/1 Mode Register Default after reset: 00H (MSB) TF1 TF1 TR1 TF0 TR0 IE1 IT1 IE0 (LSB) IT0 TCON SFR-Address 88H
Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify edge/low level triggered external interrupts.
TR1 TF0
TR0 IE1 IT1 IE0 IT0
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.6 .
CDC = 0 Machine Cycles CDC = 1
OSC
. 12 .
C/T = 0 C/T = 1 T0 Pin Control
TL0 (5 Bits)
TH0 (8 Bits)
TF0
Interrupt
TR0 Gate INT0 Pin 1
_ <1
&
UES04602
Figure 25 Timer/Counter 0 Mode 0: 13-Bit Counter
. .6
CDC = 0 Machine Cycles CDC = 1
OSC
. 12 .
C/T = 0 C/T = 1 T0 Pin Control
TL0 (8 Bits)
TF0
Interrupt
TR0 Gate INT0 Pin 1
_ <1
&
Reload
TH0 (8 Bits)
UES04603
Figure 26 Timer/Counter 0 Mode 2: 8-Bit Auto-Reload
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. .6
CDC = 0 Machine Cycles CDC = 1
fm
OSC fm
. . 12
C/T = 0 C/T = 1 T0 Pin TR0 Gate INT0 Pin fm TR 1 Control 1
_ <1
TL0 (8 Bits) Control &
TF 0
Interrupt
TH0 (8 Bits)
TF1
Interrupt
UES04604
Figure 27 Timer/Counter 0 Mode 3: Two 8-Bit Counters
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6.3.8
Watchdog Timer
To protect the systems against software upset, the user's program has to clear this watchdog within a previously programmed time period. If the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. The watchdog timer is a 15-bit timer, which is incremented by a count rate of either fCYCLE/2 or fCYCLE/128. The latter is enabled by setting bit WDTREL.7. Note, that fCYCLE can be fQuarz/12 for CDC = 1 or fQuarz/6 for CDC = 0 (see Chapter "Advanced Function Register" on page 115). Immediately after start, the watchdog timer is initialized to the reload value programmed to WDTREL.0 - WDTREL.6. After an external reset register WDTREL is cleared to 00H. The lower seven bits of WDTREL can be loaded by software at any time. The watchdog timer is started by software by setting bit SWDT in special function register WDCON (bit 6). If the counter is stopped, and WDTREL is loaded with a new value, WDTH (high-byte of the watchdog timer) is updated immediately. WDTL (low-byte of the watchdog timer) is always zero, if the counter is stopped. Once started the watchdog timer cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT (AFR.6) and by the next instruction setting SWDT (WDCON.6). Bit WDT will automatically be cleared during the third machine cycle after having been set. This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog. If the software fails to clear the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFFH. The duration of the reset signal then depends on the prescaler selection. This internal reset differs from an external reset only in so far as the watchdog timer is not disabled and bit WDTS (WDCON.7) is set. Bit WDTS allows the software to examine from which source the reset was activated. The watchdog timer status flag can also be cleared by software. With WDTREL = 80H and an oscillator frequency of 18 MHz the maximum time period is about 0.7 s for CDC = 0 and about 1.4 s for CDC = 1.
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Watchdog Timer Control Bits Watchdog Timer Reload Register Default after reset: 00H (MSB) (LSB)
WDTREL.7 WDTREL.6 WDTREL.5 WDTREL.4 WDTREL.3 WDTREL.2 WDTREL.1 WDTREL.0
WDTREL
SFR-Address 86H
WDTREL.7 WDTREL.0 WDTREL.6
Prescaler bit. When set, the watchdog is clocked through an additional divide-by-64 prescaler. Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT. WDCON SFR-Address A7H
Watchdog Timer Control Register Default after reset: 00H (MSB) WDTS WDTS SWDT - -
(LSB) - - - -
Watchdog timer reset flag. If bit WDTS is `1' after reset, the reset has been initiated by the watchdog timer. After external reset, WDTS is reset to `0'. Watchdog timer start flag. Set to activate the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed.
SWDT
WDCON.0 - WDCON.5 Reserved.
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Advanced Function Register AFR Advanced Function Register Default after reset: 00xxxxxxB (MSB) CDC CDC WDT WDT 0 0 0 0 0 (LSB) 0 AFR SFR-Address A6H
See Chapter "Advanced Function Register" on page 115. Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT (WDCON.6) is set to the watchdog timer. Reserved, always to be written with `0'.
AFR.0 - AFR.5
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6.3.9
Capture Compare Timer
For easier infrared signal decoding, an additional Capture Compare Timer is implemented. A functional overview is given in following feature list: - - - - - - - - 16-Bit-Counter with 2 or 3 prescaler bits selectable via SFR Counting rate: internal clock (18 MHz) Counter reloadable, prescaler bits reload with `0' Capture function Timer polling mode P3.3 or P3.2 selectable as capture input Capture on rising and/or falling edge Overflow-Bit
Infrared Timer Control Register IRTCON Infrared Timer Control Register Default after reset: 00H (MSB) OV OV PR PLG PR PLG REL RUN RISE FALL (LSB) SEL IRTCON SFR-Address E5H
will be set by hardware, if counter overflow has occurred; must be cleared by software if cleared, 2-bit prescaler; if set, 3-bit prescaler if set, Timer polling mode selected, capture function is automatically disabled, reading capture registers will now show current timer value if set, counter will be reloaded simultaneously with capture event run/stop the counter capture (and if REL=`1', reload) on rising edge capture (and if REL=`1', reload) on falling edge if set, P3.3 is selected for capture input, otherwise P3.2
REL RUN RISE FALL SEL
Note: If counter is halted, a counter-reload with the contents of the reload registers is forced by hardware to give the counter a starting value.
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The registers RELH and RELL (SFR-address E2H and E1H) are the reload registers, CAPH and CAPL (SFR-addresses E4H and E3H) are the corresponding capture registers. The reset value of these registers is undefined. 6.3.10 Serial Interface
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The frequencies and baud rates described in this chapter depend on the internal system clock, used by the serial interface. The internal system clock frequency of the serial interface is defined by the oscillator frequency fOSC and the setting of bit CDC in the Advanced Function Register AFR of the special function registers (see Chapter "Advanced Function Register" on page 115). The serial port can operate in 4 modes: Mode 0: Mode 1: Serial data enters and exits through RxD (P3.6). TxD (P3.7) outputs the shift clock. 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in special function register SCON. The baud rate is variable. 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On reception, the 9th data bit goes into RB8 in the special function register SCON, while the stop bit is ignored. The baud rate is programmable via SFR-Bit SMOD. 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1 ). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable.
Mode 2:
Mode 3:
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Serial Port Control Register SCON Serial Port Control Register Default after reset: 00H (MSB) SM0 SM0 SM1 SM2 SM1 SM2 REN TB8 RB8 TI (LSB) RI SCON SFR-Address 98H
Serial Port Mode Selection, see Table 22. Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through stop bit time in the other modes, in any serial reception. Must be cleared by software.
REN TB8 RB8
TI
RI
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Table 22 Serial Port Mode Selection SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift Reg. 8-bit UART 9-bit UART 9-bit UART Baud Rate (CDC = 0) fOSC/6 Variable fOSC/32, fOSC/16 Variable
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in mode 0 by the condition Rl = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. The control, mode, and status bits of the serial port in special function register SCON are illustrated on page 92. 6.3.10.1 Multiprocessor Communication
Modes 2 and 3 of the serial interface of the controller have a special provision for multiprocessor communication. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor communications is as follows. When the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
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6.3.10.2
Baud Rates
The baud rate in mode 0 is fixed: Mode 0 baud rate = -------------6 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON (bit 7). If SMOD = 0 (which is the value on reset), the baud rate is 1/32 of the oscillator frequency. If SMOD = 1, the baud rate is 1/16 of the oscillator frequency. 2 Mode 2 baud rate = ----------------- x f OSC 32 The baud rates in modes 1 and 3 are determined by the timer 1 overflow rate or can be generated by the internal baud rate generator. When timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows: 2 Mode 1, 3 baud rate = ----------------- x Time 1 overflow 16 The timer 1 interrupt should be disabled in this application. The timer itself can be configured for either "timer" or "counter" operation, and in any of the 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case, the baud rate is given by the formula:
SMOD SMOD
f OSC
f OSC 2 Mode 1, 3 baud rate = ----------------- x --------------------------------------------16 12 x ( 256 TH1 )
One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the timer 1 interrupt to do a 16-bit software reload.
SMOD
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6.3.10.3
More about Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/ received: 8 data bits (LSB first). Figure 28 shows a simplified functional diagram of the serial port in mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and tells the TX-control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write-to-SBUF" and activation of SEND. SEND enables the output of the shift register to the alternate output function line of P3.6, and also enables SHIFT CLOCK to the alternate output function, line of P3.7. At the end of every machine cycle in which SEND is active, the contents of the transmit shift register is shifted one position to the right. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX-control block to do one last shift and then deactivate SEND and set Tl. Both of these actions occur in the 10th machine cycle after "write-to-SBUF". Reception is initiated by the condition REN = 1 and Rl = 0. At the end of the next machine cycle, the RX-control unit writes the bits `1111 1110' to the receive shift register, and the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.7. At the end of every machine cycle in which RECEIVE is active, the contents of the Receive Shift register are shifted one position to the left. The value that comes in from the right is the value that was sampled at the P3.6 pin in the same machine cycle. As data bits come in from the right, 1 s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX-control block to do one last shift and load SBUF. In the 10th machine cycle after the write to SCON that cleared Rl, RECEIVE is cleared and Rl is set. 6.3.10.4 More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first) and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The baud rate is determined by the timer 1 overflow rate. Figure 30 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-to SBUF" signal also loads a `1' into the 9th bit position of the transmit shift register and flags the TX- control block that a transmission is requested. Transmission actually
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commences at the beginning of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-SBUF" signal). The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX-control unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 10th divide-by-16 rollover after "write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1 FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1 s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX-control block to do one last shift, load SBUF and RB8, and set Rl. The signal to load SBUF and RB8, and to set Rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. Rl = 0, and 2. either SM2 = 0 or the received stop bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF and Rl is activated. At this time, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition in RxD. 6.3.10.5 More about Modes 2 and 3
11 bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit, (1). On transmission, the 9th data bit (TB8) can be assigned the value of 0 or 1. On reception, the 9th data bit goes into RB8 in SCON.
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Figures 32 and 34 show a functional diagram of the serial port in modes 2 and 3 and associated timings. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-to- SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX- control unit that a transmission is requested. Transmission commences at the beginning of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-SBUF" signal). The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just left of the TB8, and all positions to the left of that contain zeros. This condition flags the TX-control unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 11th divide-by-16 rollover after "write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1 s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the RX-control block to do one last shift, load SBUF and RB8, and set Rl. The signal to load SBUF and RB8, and to set Rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. Rl = 0, and 2. either SM2 = 0 or the received 9th data bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost, and Rl is not set. If both conditions are met, the received 9th data bit goes into RB8, the first 8 data bits go into SBUF. One bit time later, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition at the RxD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8 or Rl.
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Internal Bus 1
Write to SBUF D S Q & SBUF
RxD P3.6 Alt. Output Function
CL
Shift Zero Detector
Start TX Control Clock TX Clock Serial Port Interrupt
_ <1
TI
Send
_ <1
&
TxD P3.7 Alt. Output Function
Shift Clock RI RX Control Receive
REN RI
& Start RX Clock
1 1 1 1 1 1 1 0 Shift RxD P3.6 Alt. Input Function
Input Shift Register Load SBUF Shift
SBUF Read SBUF Internal Bus
UES04726
Figure 28 Serial Port Mode 0, Functional Diagram
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Figure 29 Serial Port Mode 0, Timing
Transmit
Semiconductor Group
D0 D1 D4 D7 D2 D3 D5 D6
Receive
Write to SBUF
Send
Shift
RxD (Data Out)
TxD (Shift Clock)
TI
99
D0 D1 D2 D3 D4 D5
Write to SCON (Clear RI)
RI
Receive
Shift D6 D7
RxD (Data In)
TxD (Shift Clock)
UED04727
SDA 525x
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SDA 525x
Internal Bus 1
Write to SBUF D S Q & SBUF
_ <1
TxD
CL
Zero Detector
Start Timer1 Overflow SMOD=1
Shift TX Control
Data Send
. 16 .
TX Clock Serial Port Interrupt
_ <1
TI
.2 .
SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector
. 16 .
RX Clock Start RX Control RI Load SBUF
1FFH Shift Bit Detector RxD Load SBUF
Input Shift Register (9 Bits) Shift
SBUF Read SBUF Internal Bus
UES04728
Figure 30 Serial Port Mode 1, Functional Diagram
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TX Clock
Figure 31 Serial Port Mode 1, Timing
Transmit
Start Bit D0 D1 D2 D4 D7 D3 D5 D6 Stop Bit / 16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
UED04729
Semiconductor Group
Write to SBUF
Send
Data
Shift
TxD
TI
101
RX Clock
RxD
Receive
Bit Detector Sample Times
Shift
RI
SDA 525x
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SDA 525x
Internal Bus TB8
Write to SBUF S D CL Zero Detector Q SBUF &
_ <1
TxD
Phase 2 CLK SMOD=1
Stop Bit Gen. Shift Start TX Control
Data Send
. 16 .
TX Clock Serial Port Interrupt
_ <1
TI
.2 .
SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector
. 16 .
RX Clock Start RX Control RI Load SBUF
1FFH Shift Bit Detector RxD Load SBUF
Input Shift Register (9 Bits) Shift
SBUF Read SBUF Internal Bus
UES04730
Figure 32 Serial Port Mode 2, Functional Diagram
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TX Clock
Figure 33 Serial Port Mode 2, Timing
Transmit
Start Bit D0 D1 D2 D4 D7 D3 D5 D6 TB8 Stop Bit / 16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit
UED04731
Semiconductor Group
Write to SBUF
Send
Data
Shift
TxD
TI
103
Stop Bit Gen.
RX Clock
RxD
Receive
Bit Detector Sample Times
Shift
RI
SDA 525x
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SDA 525x
Internal Bus TB8
Write to SBUF D S Q & SBUF
_ <1
TxD
CL
Zero Detector
Start Timer1 Overflow SMOD=1
Shift TX Control
Data Send
. 16 .
TX Clock Serial Port Interrupt
_ <1
TI
.2 .
SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector
. 16 .
RX Clock Start RX Control RI Load SBUF
1FFH Shift Bit Detector RxD Load SBUF
Input Shift Register (9 Bits) Shift
SBUF Read SBUF Internal Bus
UES04732
Figure 34 Serial Port Mode 3, Functional Diagram
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Figure 35 Serial Port Mode 3, Timing
Transmit
Start Bit D0 D1 D2 D4 D7 D3 D5 D6 TB8 Stop Bit / 16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit
UED04733
Semiconductor Group
TX Clock
Write to SBUF
Send
Data
Shift
TxD
105
TI
RX Clock
RxD
Receive
Bit Detector Sample Times
Shift
RI
SDA 525x
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SDA 525x
6.3.11
Pulse Width Modulation Unit (PWM)
The on-chip-PWM unit consists of 6 quasi-8-Bit and 2 quasi-14-Bit PWM channels. Controlled via special function registers, each channel can be enabled individually. The base frequency of an 8-Bit channel is derived from the overflow of a 6-Bit counter which counts internal clocks. On every counter overflow, the enabled PWM lines will be set to one (exception: compare values are zero) and will be reset when the 6 MSBs of the PWCOMPx-register match the counter value. To get an overall resolution of 8 bit, the high-time is stretched periodically, depending on the 2 LSBs of the PWCOMPx-register. For example, if PWCOMPx[1:0] is `10', the high-time will be stretched in every second base cycle. This type of PWM channel is called "6 plus 2". Table 23 Effect of PWCOMPx-Bits for 8-Bit PWM PWCOMPx Bit 1 Bit 0 Cycle Number `Stretched' 1,3 2
`stretched'
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Figure 36 Simplified Example with PWCOMPx[1:0]= `10' The function of an 14-Bit channel is very similar. Here, an 8-Bit counter gives the base frequency. All 8 bits of the PWCOMPx registers are compared with the counter value, and the value in PWEXTx register gives the number of stretchings within 64 successive base cycles. Thus, this type of PWM channel is called "8 plus 6". The Table 24 shows the influence of the PWEXTx register bits on cycles to be stretched.
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Table 24 Effect of PWEXTx-Bits for 14-Bit PWM PWEXTx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Cycle Number `Stretched' 1,3,5,7,...,59,61,63 2,6,10,...,54,58,62 4,12,20,...,52,60 8,24,40,56 16,48 32 no effect no effect
Table 25 Base frequencies PWM Resolution 8 bit 14 bit Base Frequency fOSC/ 2CDC x 64 fOSC/ 2CDC x 256
Further Details of the PWM Unit The PWM-output channels are placed as alternate functions to the eight lines of port 1. P1.0 ... P1.5 contain the 6 output channels with 8-bit resolution and P1.6 ... P1.7 the 2 output channels with 14-bit resolution. Each PWM-channel can be individually switched between PWM-function and port function. The six 8-bit compare registers PWCOMP0 - PWCOMP5 are located at SFR-addresses 0F1H - 0F6H. The two 14-bit compare registers consist each of an 8-bit register PWCOMP6 or PWCOMP7 and of a six-bit extension register PWEXT6 or PWEXT7, all located at SFR-addresses 0FAH - 0FDH. They contain the modulation ratios of the output signals, which are related to the maximum, defined by the counter's resolution. These compare registers are double buffered and a new compare value will only be taken into the main register, after the next timer overflow or if the PWM-timer is stopped. The PWM-timer registers located at SFR-address F7 and F9H contain the actual value of the PWM-counter low byte and high byte and can only be read by the CPU. Every compare register, which is not employed for the PWM-output can be used as an additional register. This is not allowed for register PWME. The internal timer of the PWM unit is running as long as at least one PWM-channel is enabled by the PWM-Enable Register PWME.
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PWM-Enable Register PWME PWM-Enable Register Default after reset: 00H (MSB) E7 E6 E5 E4 E3 E2 E1 (LSB) E0 PWME SFR-Address F8H
E7 - E0
=0 =1
The corresponding PWM-channel is disabled. P1.i functions as normal bidirectional I/O-port. He corresponding PWM-channel is enabled. E0...E5 are channels with 8-bit resolution, while E6 and E7 are channels with 14-bit resolution.
PWM Compare Registers PWCOMP 0 - 5 PWM Compare Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PWCOMP 0 - 5 SFR-Address F1H-F6H
Bit 7 - Bit 2
This bits define the high time of the output. If all bits are 0, the high time is 0 internal clocks. If all bits are 1, the high time is 63 internal clocks. If this bit is set, every second PWM-Cycle is stretched by one internal clock, regardless of the settings of Bit7...Bit2. If this bit is set, every fourth PWM-Cycle is stretched by one internal clock, regardless of the settings of Bit7...Bit2.
Bit 1 Bit 0
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PWM Compare Registers PWCOMP 6, 7 PWM Compare Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PWCOMP 6, 7 SFR-Address FBH,FDH
Bit 7 - Bit 0
This bits define the high time of the output. If all bits are 0, the high time is 0 internal clocks. If all bits are 1, the high time is 255 internal clocks.
PWM Extension Registers PWEXT 6, 7 PWM Extension Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PWEXT 6, 7 SFR-Address FAH,FCH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1, Bit 0
If this bit is set, every second PWM-Cycle is stretched by one internal clock. If this bit is set, every fourth PWM-Cycle is stretched by one internal clock. If this bit is set, every eighth PWM-Cycle is stretched by one internal clock. If this bit is set, every 16th PWM-Cycle is stretched by one internal clock. If this bit is set, every 32th PWM-Cycle is stretched by one internal clock. If this bit is set, every 64th PWM-Cycle is stretched by one internal clock. This bits have to be set to 0.
Note: The described operation is independent of the setting of PWCOMP6 or PWCOMP7. The stretch operation is interleaved between PWM-Cycles.
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PWM Low Counter Registers PWCL PWM Low Counter Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PWCL SFR-Address F7H
Bit 7 - Bit 0
This bits are the low order 8 Bits of the 14 Bit PWM-Counter. This register can only be read.
PWM High Counter Registers PWCH PWM High Counter Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PWCH SFR-Address F9H
Bit 7, Bit 6 Bit 5 - Bit 0
This bits are undefined. This bits are the high order 6 Bits of the 14 Bit PWM-Counter. This register can only be read.
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PWM-Timer
E7
E6
Enable Register
E1
E0
PWM-Channel 0 8 Bit
P 1.0
PWM-Channel 1 8 Bit
P 1.1
PWM-Channel 2 8 Bit
P 1.2
PWM-Channel 3 8 Bit
P 1.3
PWM-Channel 4 8 Bit
P 1.4
PWM-Channel 5 8 Bit
P 1.5
PWM-Channel 6 14 Bit 8 PWM-Channel 7 14 Bit
UED09860
P 1.6
P 1.7
Internal Bus
Figure 37 Block Diagram of Pulse Width Modulation Unit
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6.3.12 - - - -
Analog Digital Converter
The controller provides an A/D-converter with the following features: 4 multiplexed input channels, which can also be used as digital inputs 8-bit resolution 8.89 to 28.4 s conversion time for 18 MHz oscillator frequency Analog reference voltages supplied by pins VDDA and VSSA
The conversion time depends on the internal master clock, used by the ADC. The clockfrequency of the internal ADC master clock is defined by the external quartz (oscillator frequency fOSC), the setting of bit CDC in the Advanced Function Register AFR of the special function registers (SFR) (see Chapter "Advanced Function Register" on page 115), and the setting of bit PSC in the ADC Control Register ADCON (SFR). Both bits are software switches to activate or deactivate clock dividers by 2. The conversion time further depends on the sample time, adjustable by bit STADC (ADC-Control Register ADCON). The conversion time can be calculated by: (2 + 4 ) x 32 x 2 x2 t conversion = --------------------------------------------------------------------------------------------f OSC For the conversion, the method of successive approximation via capacitor array is used. There are three user-accessible special function registers: ADCON, ADDAT and DAPR. Special function register ADCON is used to set the operation modes, to check the status and to select one of four input channels. ADCON contains two mode bits. Bit ADM is used to choose the single or continuous conversion method. In single conversion mode (ADM = 0) only one conversion is performed after starting, while in continuous conversion mode (ADM = 1) a new conversion is automatically started on completion of the previous one. The busy flag BSY (ADCON.4) is automatically set when a conversion is in progress. After completion of the conversion it is reset by hardware. This flag can be read only, a write has no effect. MX0 and MX1 are used to select one of 4 A/Dchannels. With PSC a divide by two prescaler for the internal master clock of the ADC can be activated. For PSC = 0 the internal chip-clock is used as master clock for the ADC. For PSC = 1 the internal chip-clock is divided by two before being used as master clock for the ADC. With bit STADC the sample time of the ADC can be varied. Bit STADC = 0 selects the normal sample time (sample time of 2 ADC master clock cycles), while for STADC = 1 the sample time is slowed down by a factor of 4 (sample time of 8 ADC master clock cycles) e.g. for high-impedance input signals. The special function register ADDAT holds the converted digital 8-bit data result. The data remains in ADDAT until it is overwritten by the next converted data. ADDAT can be read or written under software control. A start of conversion is triggered by a write-to DAPR instruction. The data written must be 00H.
2 x STADC
CDC PSC
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/6 CDC = 1 Internal Chip Clock CDC = 0 /2
Machine Cycles, Instruction Cycles PSC = 0 Internal System Clock for ADC PSC = 1
UES09861
/2 OSC
Figure 38 Internal System Clock of the ADC ADC-Start Register DAPR ADC-Start Register Default after reset: 00H (MSB) - - - - - - - (LSB) - DAPR SFR-Address DAH
Only the address of DAPR is used to decode a start-of-conversion signal. No bits are implemented. A read from DAPR might show random values.
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ADC-Control Register ADCON ADC-Control Register Default after reset: 00H (MSB) PSC STADC IADC BSY ADM 0 MX1 (LSB) MX0 ADCON SFR-Address D8H
This register is bit addressable. PSC Prescaler control: PSC = 0 for prescaler not active. Internal master clock of ADC is equal to the internal chip clock. PSC = 1 for prescaler active. Internal master clock of ADC is at half the internal chip clock. ADC sample time adjustment: STADC = 0 for normal sample time. STADC = 1 for fourfold sample time. ADC interrupt request flag. Set on completion of ADconversion. Must be cleared by software. Busy flag; = 1, during conversion. ADC-conversion mode: ADM = 0 for single and ADM = 1 for continuous conversion. Always to be written with `0'. ADC-channel select.
STADC IADC BSY ADM ADCON.2 MX1, MX0 Table 26 ADC-Channel Select MX1 0 0 1 1 MX0 0 1 0 1
Selected Channel 0 1 2 3
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ADC-Data Register ADDAT ADC-Data Register Default after reset: undefined (MSB) AD7 AD6 AD5 AD4 AD3 AD2 AD1 (LSB) AD0 ADDAT SFR-Address D9H
AD (7-0) 6.3.13
8-Bit Analog Data Value Advanced Function Register AFR SFR-Address A6H (LSB) WDT 0 0 0 0 0 0
Advanced Function Register Default after reset: 00xxxxxxB (MSB) CDC
CDC
Clock divider control bit. If set, the clock divider is on. The internal clock frequency is half the external oscillator frequency. If cleared, the clock divider is off. The internal clock frequency is equal to the external oscillator frequency. This feature can be used to reduce power dissipation by reducing the internal clock frequency by a factor of two. See Chapter "Watchdog Timer" on page 87. Reserved, always to be written with `0'.
WDT AFR.0 - AFR.5
The machine cycle time is controlled by bit CDC too. For CDC = 1 a machine cycle consists of 12 oscillator cycles and for CDC = 0 of six oscillator cycles (see Figure 14).
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6.3.14
Instruction Set
The assembly language uses the same instruction set and the same instruction opcodes as the 8051 microcomputer family. 6.3.14.1 Rn direct @Ri #data #data 16 bit Notes on Data Addressing Modes - - - - - - Working register R0 - R7. 128 internal RAM-locations, any I/O-port, control or status register. Indirect internal RAM-location addressed by register R0 or R1. 8-bit constant included in instruction. 16-bit constant included as bytes 2 & 3 of instruction. 128 software flags, any I/O-pin, control or status bit in special function registers.
Operations working on external data memory (MOVX ...) are used to access the extended internal data RAM (XRAM). 6.3.14.2 addr 16 addr 11 rel Notes on Program Addressing Modes - - - Destination address for LCALL & LJMP may be anywhere within the program memory address space. Destination address for ACALL & AJMP will be within the same 2 Kbyte of the following instruction. SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127/ - 128 bytes relative to first byte of the following instruction.
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6.3.14.3
Instruction Set Description
Table 27 Arithmetic Operations Mnemonic ADD ADD ADD ADD A, Rn A, direct A, @Ri A, #data Description Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with Carry flag Add direct byte to A with Carry flag Add indirect RAM to A with Carry flag Add immediate data to A with Carry flag Subtract register from A with Borrow Subtract direct byte from A with Borrow Subtract indirect RAM from A with Borrow Subtract immediate data from A with Borrow Increment Accumulator Increment register Increment direct byte Increment indirect RAM Decrement Accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A & B Divide A & B Decimal Adjust Accumulator Byte 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1
ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A, Rn A, direct A, @Ri A, #data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A
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Table 28 Logical Operations Mnemonic ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A A A A A A Description AND register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive-OR register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte Exclusive-OR immediate data to direct Clear Accumulator Complement Accumulator Rotate Accumulator left Rotate A left through the Carry flag Rotate Accumulator right Rotate A right through Carry flag Swap nibbles within the Accumulator Byte 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1
SWAP A
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Table 29 Data Transfer Operations Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV A, Rn A, direct A, @Ri A, #data Rn, A Rn, direct Rn, #data direct, A direct, Rn direct, direct direct, @Ri direct, #data @Ri, A @Ri, direct @Ri, #data DPTR, #data 16 Description Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to Accumulator Move Code byte relative to PC to Accumulator Move External RAM (8-bit addr) to Accumulator1) Move External RAM (16-bit addr) to Accumulator Move A to External RAM (8-bit addr) Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order digital indirect RAM with A1)
1)
Byte 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
MOVC A@A + DPTR MOVC A@A + PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP XCH XCH XCH direct A, Rn A, direct A, @Ri
Move A to External RAM (16-bit addr)
XCHD A, @Ri
1)
not applicable for the SDA525x
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Table 30 Boolean Variable Manipulation Mnemonic CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C, bit C, /bit C, bit C, /bit C, bit bit, C Description Clear Carry flag Clear direct bit Set Carry flag Set direct bit Complement Carry flag Complement direct bit AND direct bit to Carry flag AND complement of direct bit to Carry OR direct bit to Carry flag OR complement of direct bit to Carry Move direct bit to Carry flag Move Carry flag to direct bit Byte 1 2 1 2 1 2 2 2 2 2 2 2
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Table 31 Program and Machine Control Operations Mnemonic ACALL addr 11 LCALL addr 16 RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr 11 addr 16 rel @A + DPTR rel rel rel rel bit, rel bit, rel bit, rel A, direct rel A, #data, rel Rn, #data, rel @Ri, #data, rel Rn, rel direct, rel Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative to the DPTR Jump if Accumulator is zero Jump if Accumulator is not zero Jump if Carry flag is set Jump if Carry flag is not set Jump if direct bit set Jump if direct bit not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Byte 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3
Compare immediate to register and jump if not equal 3 Compare immediate to indirect and jump if not equal 3 Decrement register and jump if not zero Decrement direct and jump if not zero No operation 2 3 1
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6.3.15
Instruction Opcodes in Hexadecimal Order
Table 32 Instruction Opcodes in Hexadecimal Order Hex Code Number of Bytes 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 1 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 Mnemonic NOP AJMP LJMP RR INC INC INC INC INC INC INC INC INC INC INC INC JBC ACALL LCALL RRC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC JB AJMP RET RL ADD Operands code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code addr code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code addr code addr A A, #data
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Table 32 Instruction Opcodes in Hexadecimal Order (cont'd) Hex Code Number of Bytes 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 Mnemonic ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD JNB ACALL RETI RLC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC JC AJMP ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL
123
Operands A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 bit addr, code addr code addr A A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr data addr., A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3
1998-04-08
Semiconductor Group
SDA 525x
Table 32 Instruction Opcodes in Hexadecimal Order (cont'd) Hex Code Number of Bytes 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 Mnemonic ORL ORL ORL ORL JNC ACALL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL JZ AJMP XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL JNZ ACALL ORL
124
Operands A, R4 A, R5 A, R6 A, R7 code addr code addr data addr, A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr. data addr, A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr C, bit addr
1998-04-08
Semiconductor Group
SDA 525x
Table 32 Instruction Opcodes in Hexadecimal Order (cont'd) Hex Code Number of Bytes 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 1 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 3 2 2 2 2 2 2 2 2 2 2 3 2 2 1 2 2 1 1 1 1 Mnemonic JMP MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV SJMP AJMP ANL MOVC DIV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB SUBB SUBB
125
Operands @A + DPTR A, #data data addr, #data @R0, #data @R1, #data R0, #data R1, #data R2, #data R3, #data R4, #data R5, #data R6, #data R7, #data code addr code addr C, bit addr A, @A + PC AB data addr, data addr data addr, @R0 data addr, @R1 data addr, R0 data addr, R1 data addr, R2 data addr, R3 data addr, R4 data addr, R5 data addr, R6 data addr, R7 DPTR, #data 16 code addr bit addr, C A, @A + DPTR A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1
1998-04-08
Semiconductor Group
SDA 525x
Table 32 Instruction Opcodes in Hexadecimal Order (cont'd) Hex Code Number of Bytes 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 1 1 1 1 1 1 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 3 3 3 3 3 3 3 3 3 3 3 2 Mnemonic SUBB SUBB SUBB SUBB SUBB SUBB ORL AJMP MOV INC MUL reserved MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE PUSH
126
Operands A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 C, /bit addr code addr C, bit addr DPTR AB @R0, data addr @R1, data addr R0, data addr R1, data addr R2, data addr R3, data addr R4, data addr R5, data addr R6, data addr R7, data addr C, /bit addr code addr bit addr C A, #data, code addr A, data addr, code addr @R0, #data, code addr @R1, #data, code addr R0, #data, code addr R1, #data, code addr R2, #data, code addr R3, #data, code addr R4, #data, code addr R5, #data, code addr R6, #data, code addr R7, #data, code addr data addr
1998-04-08
Semiconductor Group
SDA 525x
Table 32 Instruction Opcodes in Hexadecimal Order (cont'd) Hex Code Number of Bytes C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 3 Mnemonic AJMP CLR CLR SWAP XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH POP ACALL SETB SETB DA DJNZ not applicable not applicable DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ MOVX AJMP not applicable not applicable CLR MOV MOV MOV
127
Operands code addr bit addr C A A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 data addr code addr bit addr C A data addr, code addr
2 2 2 2 2 2 2 2 1 2
R0, code addr R1, code addr R2, code addr R3, code addr R4, code addr R5, code addr R6, code addr R7, code addr A, @DPTR code addr
1 2 1 1
A A, data addr A, @R0 A, @R1
1998-04-08
Semiconductor Group
SDA 525x
Table 32 Instruction Opcodes in Hexadecimal Order (cont'd) Hex Code Number of Bytes E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 1 1 1 1 1 1 1 1 1 2 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOVX ACALL not applicable not applicable CPL MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV Operands A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 @DPTR, A code addr
1 2 1 1 1 1 1 1 1 1 1 1
A data addr, A @R0, A @R1, A R0, A R1, A R2, A R3, A R4, A R5, A R6, A R7, A
Semiconductor Group
128
1998-04-08
SDA 525x
7 7.1 Table 33 Parameter
Electrical Characteristics Absolute Maximum Ratings Symbol VS Ptot TA Tstg Limit Values - 0.5 to 7 1 0 to 70 - 65 to 125 Unit V W C C
Voltage on any pin with respect to ground (VSS) Power dissipation Ambient temperature under bias Storage temperature 7.2 DC-Characteristics
Table 34 DC-Characteristics TA = 0 to 70 C; VDD = 5 V 10 %, VSS = 0 V(CL = 80 pF) Parameter L-input voltage (all except SC) H-input voltage (all except XTAL1, SC) H-input voltage (XTAL1,LCIN) L-output voltage Symbol
VIL VIH VIH1 VOL
Limit Values min. - 0.5 2.0 0.7 VDD - 2.4 2.4 max. 0.8
VDD + 0.5 VDD + 0.5
Units Test Condition V V V V V V A A mA mA IOL = 3.2 mA IOH = - 40 A IOH = -1.6 mA VIN = 0.45 V 0.45 V VIN VDD VDD = 5 V; fOSC = 18 MHz VDD = 5 V; fOSC = 18 MHz
1998-04-08
0.45 - - - 50 1 85 45
H-output voltage (ports 1 - 4 VOH in port-mode) H-output voltage (all except ports in port-mode) Logical 0 input current (ports 1 - 4, RST,VS)
VOH1 IIL1
Input leakage current (port 0, ILI port 2, HS/SC) Power supply current IDD (Sum of VDD- and VDDA-Pins) Idle current IIDLE (Sum of VDD- and VDDA-Pins)
Semiconductor Group 129
SDA 525x
Table 34 DC-Characteristics (cont'd) TA = 0 to 70 C; VDD = 5 V 10 %, VSS = 0 V(CL = 80 pF) Parameter Symbol Limit Values min. Power down current IPD (Sum of VDD- and VDDA-Pins) Pin capacitance H-SC voltage L-SC voltage 1 L-SC voltage 2 Analog input capacitance ADC-total unadjusted error Analog ground voltage Analog reference voltage Analog input voltage Video input signal level Synchron signal amplitude Data amplitude
1)
max. 1.5 10
Units Test Condition mA pF V V V pF LSB V V V V V V VDD = 5 V fC = 1 MHz
CIO VSCH VSCL1
VSCL2
1)
VDD + 0.5
1) 1)
- 0.5
1)
CI TUE VSSA VDDA VAI VCVBS VSYNC VDAT VSS VDD VSS - 0.2 0.7 0.2 0.3
45 t.b.d. VSS VDD VDD + 0.2 2.0 1.0 1.0
adjustable, see Chapter "Sandcastle Decoder" on page 33 and figure 41.
Semiconductor Group
130
1998-04-08
SDA 525x
7.3
AC-Characteristics
External Clock Drive XTAL1 / Quartz Clock Drive XTAL1 - XTAL2 Table 35 TA = 0 to 70 C; VDD = 5 V 10 %, VSS = 0 V (CL = 80 pF) Parameter Symbol Limit Values Fixed internal Clock 1/tCLCL = 18 MHz min. Cycle time Address out to valid instr in Oscillator period External clock high time External clock low time External clock rise time External clock fall time tCY tAVIV tCLCL tCHCX tCLCX tCLCH tCHCL 6 tCLCL - 55.6 13 13 - - - 2.3. x tCLCL - - - 13 13 max. ns ns ns ns ns ns ns Unit
t CHCX VDD-0.5
0.7 VDD 0.2 VDD-0.1
t CLCH
t CHCL
t CLCX t CLCL
UED04735
Figure 39 External Clock Cycle
Semiconductor Group
131
1998-04-08
SDA 525x
t CY t ALAH
ALE
t ALIV
t PXIX
Inst IN
t PXAV
D
Inst IN
Inst IN
t AVIV
A A0-16 A0-16
UED04734
Figure 40 Program Memory Read Cycle
Semiconductor Group
132
1998-04-08
SDA 525x
OSD-Input/Output Timing Table 36 Parameter Symbol Limit Values Fixed DOT Clock fDOT = 12 MHz min. L-sandcastle time H-sandcastle time Horizontal offset Pixel width tSCL tSCH tHO tDOT 15 3 tSCH 83 max. s s s ns Unit
t VO
SC
t SCL
VSCH VSCL 2 VSCL 1
R, G, B, BLAN, COR
t HO
t SCH
t DOT t LINE
UET05095
Figure 41 OSD-Input/Output Timing
Semiconductor Group
133
1998-04-08
SDA 525x
Display-Generator-Timing Table 37 TA = 0 to 70 C; VDD = 5 V 10 %, VSS = 0 V Parameter Hsync width End of visible screen area to Hsync `1' Start of visible screen area to Hsync `0' Delay between Hsync and R/G/B/BLAN/COR-lines
1)
Symbol tHHHL tVLHH tHLVH tHHCL
Limit Values min. 2.8 / 1.41) 0 0 25 - - - 100 max.
Unit s ns ns ns
default after reset is 2.8 s; if bit 7 in SFR 0CDH is set, the second value is valid
Horizontal Flyback
Visible Area
tHHHL
HS applied to SDA525x R/G/B/BLAN/ COR
tVLHH tHLVH
tHHCL
Figure 42 Horizontal Sync-Timing
Semiconductor Group
134
1998-04-08
SDA 525x
AC-Testing Input, Output, Float Waveforms AC testing inputs are driven at VDD - 0.5 V for a logic `1' and at 0.45 V for a logic `0'. Timing measurements are made at VIHmin for a logic `1' and at VIHmax for a logic `0'. For timing purposes a port pin is no longer floating, when a 100 mV change from load voltage occurs.
VDD - 0.5 V
0.45 V
0.2 VDD + 0.9 Test Points 0.2 VDD - 0.1
VLOAD + 0.1 V VLOAD VLOAD 0.1 V Timing Reference Points
VOH - 0.1 V VOL + 0.1 V
UED04592
Figure 43 I/O-Waveform for AC-Tests
Semiconductor Group
135
1998-04-08
SDA 525x
8
Applications
EPROM D
A0...A16 D0...D7
A
A17, A18
33 pF XTAL1 18 MHz 33 pF XTAL2 +5 V 8.2 k 10 F RST SDA 525x
P0.0-7 P1.0-7 P2.0-3 P3.0-7 CVBS
8 8 4 8
I/O Port 0 (Open-Drain) I/O Port 1 (PWM) Input Port 2 (ADC) I/O Port 3 330 nF CVBS (1VPP) 470 k 150 pF 2.2 k
6.8 k 33 nF FIL1 6.8 k 33 nF FIL2 8.2 k 220 nF LCIN FIL3 R/G/B BLAN/COR LCOUT SC 3 2 Sandcastle
39 pF
6.8 H 39 pF max. tolerance of LC-circuit 82 k
REF
VDD
VSS
10 F
+5 V Only ROMless
UED09863
Figure 44 Application Circuit for 50 Hz Field Frequency
Semiconductor Group 136 1998-04-08
SDA 525x
9
Package Outlines
P-SDIP-52-1 Plastic Shrink Dual In-line Package
0.5 min 4.83 max
15.24 +0.7
3.43 -0.4
1.78
1.3 max
0.46 0.1
0.25
M
52x
0.25 0.05 14.02 0.25 15.24 +1.7
52
27
1
46.1 -0.3
26
0.25 max
GPD05262
Index Marking
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 137
Dimensions in mm 1998-04-08
SDA 525x
P-LCC-84-2 (Plastic Leaded Chip Carrier)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 138
Dimensions in mm 1998-04-08
GPL05620
SDA 525x
P-MQFP-64-1 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 139
Dimensions in mm 1998-04-08
GPM05250
SDA 525x
P-MQFP-80-1 (Plastic Metric Quad Flat Package)
0.25 min 2 +0.1 -0.05 2.45 max
0.65 0.3 0.08 12.35 17.2 14
1)
0.88
C 0.12
0.1
M
A-B D C 80x
0.2 A-B D 80x 0.2 A-B D H 4x D
A
B
14 1) 17.2
80 1 Index Marking
0.6x45
GPM05249
1) Does not include plastic or metal protrusions of 0.25 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 140
Dimensions in mm 1998-04-08
7max
H
0.15 +0.08 -0.02
SDA 525x
10
Index
A ACC, A 60 AC-Characteristics 131 ACQMS_1 61 ACQMS_2 61 ACQSIR 19, 61 Acquisition 5, 16 Acquisition Control Registers 18 Acquisition hardware 16 Acquistion Mode and Status Register 18 ADC-Control Register 114 ADC-Data Register 115 ADCON 61, 114 ADC-Start Register 113 ADDAT 61, 115 Addressing Modes 47 Advanced Function Register 89, 115 AFR 89, 115 Analog Digital Converter 61 Applications 136 Architecture 42 Arithmetic Operations 117 Arithmetic Registers 60 B B 60 Banking 50 Base-Register plus Index Register-Indirect Addressing 48 Baud Rates 94 Block Diagram 7 Boolean Variable Manipulation 120 C CAPH 60 CAPL 60 Capture Compare Timer 46, 90 Capture Compare Timer Registers Character generator 22 Clear page logic 20 CPU-Hardware 43 CPU-Timing 46
Semiconductor Group
D DAPR 61, 113 Data Pointer 45 Data Transfer Operations 119 DC-Characteristics 129 DCCP 62 DCRP 62 DHD 62 Direct Addressing 48 Display 5 Display Control Registers 62 Display cursor 20 Display format and timing 20 Display generator 20 Display page addressing 21 Display special function registers Display-Generator-Timing 133 DMOD 62 DMODE1 62 DMODE2 62 Double Size 26 Double Width 26 DPH 60 DPL 60 DPSEL 60 DPTR 45 DTCR 62 DTIM 62 DVD 62 E External Interrupts 72
24
F Features 5 Flash 20 Full screen background colour Functional description 16
20
60
G General Purpose Timers/Counters H Horizontal Sync-Timing 134
80
141
1998-04-08
SDA 525x
I I/O-Port Registers 60 IE 60 Immediate Addressing 48 Infrared Timer Control Register 90 Instruction Opcodes in Hexadecimal Order 122 Instruction Set 116 Instruction Set Description 117 Internal Data Memory Address Space 57 Internal Data RAM 43, 55 Interrupt Control 63 Interrupt Control Registers 60 Interrupt Logic 45 Interrupt Nesting 71 Interrupt Sources 62 Interrupt System 62, 66 IP0 60 IP1 60 IRCON 60 IRTCON 60 L LANGC 29, 62 Language Control Register Logical Operations 118
29
M Memory Extension 50 Memory Interface 17 Memory Organization 49 Microcontroller 6, 42 Multiprocessor Communication O On Screen Display 22 OSD 22 OSD-Input/Output Timing P P0 P1 P2 P3 P4 60 60 60 60 60
93
133
Package Outlines 137 PCON 60, 77 Pin Configuration 8 Pin Functions 12 Plastic Package 137 P-LCC-84-2 138 P-LCC-84-2 Package 6 P-MQFP-64-1 6, 139 P-MQFP-80-1 140 P-MQFP-80-1 Package 6 Port 0 45 Port 1 45 Port 2 45 Port 3 45 Port 4 45 Ports and I/O-Pins 78 Power Control Register 77 Power-Down Operations 76 Priority within Level 71 Processor Reset 75 Program and Machine Control Operations 121 Program Memory 49 Program Status Word 44 P-SDIP-52-1 137 P-SDIP-52-1 Package 6 PSW 44, 60 Pulse Width Modulation Unit 46, 106 Pulse Width Modulator Registers 61 PWCH 61, 111 PWCL 61 PWCOMP 0-5 108 PWCOMP0 61 PWCOMP1 61 PWCOMP2 61 PWCOMP3 61 PWCOMP4 61 PWCOMP5 61 PWCOMP6 61 PWCOMP7 61 PWEXT6 61 PWEXT7 61 PWM 106
1998-04-08
Semiconductor Group
142
SDA 525x
PWM Compare Registers 108 PWM High Counter Registers 111 PWME 61, 108 PWM-Enable Register 108 R Read-Modify-Write 80 Register Addressing 48 Register-Indirect Addressing RELH 60 RELL 60 Response Time 74
48
Timer 0/1 Registers 60 Timer/Counter 0 81 Timer/Counter 0/1 45 Timer/Counter 1 82 TL0 60 TL1 60 TMOD 60, 83, 84 TTXSIR 62, 67 V VTX/VPS slicer 16
S Sandcastle Control Register 33 Sandcastle Decoder 33 SBUF 61 SCCON 33, 62 SCON 61, 92 Serial Interface 45, 91 Serial Interface Registers 61 Serial Port Control Register 92 Serial Port Mode 0 98 Serial Port Mode 1 100 Serial Port Mode 2 102 Serial Port Mode 3 104 Serial Port Mode Selection 93 Slicer Control Registers 61 SP 45, 60 Special Function Register Bit Address Space 59 Special Function Register Overview 60 Stack Pointer 45 Synchronisation 6 System Control Registers 60 T TCON 60 Teletext Sync Interrupt Request Register 67 Teletext Sync Signal Interrupt System 65 Teletext-Sync-Interrupt-Register 32 TH0 60 TH1 60
Semiconductor Group
W Watchdog Timer 46, 87 Watchdog Timer Control Register Watchdog Timer Registers 60 Watchdog Timer Reload Register Waveforms 135 WDCON 60 WDTH 60 WDTL 60 WDTREL 60, 88
88 88
143
1998-04-08

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